From patchwork Mon Aug 1 16:33:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jason Liu X-Patchwork-Id: 107782 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DF436B700E for ; Tue, 2 Aug 2011 02:33:50 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4AE09281E8; Mon, 1 Aug 2011 18:33:49 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yBAU865fRJPy; Mon, 1 Aug 2011 18:33:48 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C7AAF281DE; Mon, 1 Aug 2011 18:33:46 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0723D281DE for ; Mon, 1 Aug 2011 18:33:45 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id inmnMzmaYXJo for ; Mon, 1 Aug 2011 18:33:44 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yx0-f172.google.com (mail-yx0-f172.google.com [209.85.213.172]) by theia.denx.de (Postfix) with ESMTPS id B10D4281D2 for ; Mon, 1 Aug 2011 18:33:41 +0200 (CEST) Received: by yxp4 with SMTP id 4so3288854yxp.3 for ; Mon, 01 Aug 2011 09:33:40 -0700 (PDT) MIME-Version: 1.0 Received: by 10.101.195.17 with SMTP id x17mr3371336anp.53.1312216420502; Mon, 01 Aug 2011 09:33:40 -0700 (PDT) Received: by 10.100.154.12 with HTTP; Mon, 1 Aug 2011 09:33:40 -0700 (PDT) In-Reply-To: <1312197486-31712-2-git-send-email-aneesh@ti.com> References: <1312197486-31712-1-git-send-email-aneesh@ti.com> <1312197486-31712-2-git-send-email-aneesh@ti.com> Date: Tue, 2 Aug 2011 00:33:40 +0800 Message-ID: From: Jason Liu To: Aneesh V Cc: u-boot@lists.denx.de, santosh.shilimkar@ti.com, albert.u.boot@aribaud.net Subject: Re: [U-Boot] [PATCH v 1/3] arm: do not force d-cache enable on all boards X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Hi, Aneesh, 2011/8/1 Aneesh V : > c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable() > to board_init_r(). This enables d-cache for all ARM boards. > As a result some of the arm boards that are not cache-ready > are broken. Revert this change and allow platform code to > take the decision on d-cache enabling. > > Also add some documentation for cache usage in ARM. > > Signed-off-by: Aneesh V > --- > MAKEALL pending. Will update the results tomorrow. > --- >  arch/arm/lib/board.c  |    8 +++----- >  arch/arm/lib/cache.c  |   12 ++++++++++++ >  doc/README.arm-caches |   40 ++++++++++++++++++++++++++++++++++++++++ >  include/common.h      |    1 + >  4 files changed, 56 insertions(+), 5 deletions(-) >  create mode 100644 doc/README.arm-caches > > diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c > index 90709d0..d093d5b 100644 > --- a/arch/arm/lib/board.c > +++ b/arch/arm/lib/board.c > @@ -446,11 +446,9 @@ void board_init_r (gd_t *id, ulong dest_addr) >        gd->flags |= GD_FLG_RELOC;      /* tell others: relocation done */ > >        monitor_flash_len = _end_ofs; > -       /* > -        * Enable D$: > -        * I$, if needed, must be already enabled in start.S > -        */ > -       dcache_enable(); > + > +       /* Enable caches */ > +       enable_caches(); > >        debug ("monitor flash len: %08lX\n", monitor_flash_len); >        board_init();   /* Setup chipselects */ > diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c > index 92b61a2..b545fb7 100644 > --- a/arch/arm/lib/cache.c > +++ b/arch/arm/lib/cache.c > @@ -53,3 +53,15 @@ void __flush_dcache_all(void) >  } >  void   flush_dcache_all(void) >        __attribute__((weak, alias("__flush_dcache_all"))); > + > + > +/* > + * Default implementation of enable_caches() > + * Real implementation should be in platform code > + */ > +void __enable_caches(void) > +{ > +       puts("WARNING: Caches not enabled\n"); > +} > +void enable_caches(void) > +       __attribute__((weak, alias("__enable_caches"))); What about the following change? #ifndef CONFIG_SYS_DCACHE_OFF dcache_enable(); #else puts("WARNING: Caches not enabled\n"); #endif This can avoid adding the duplicated cache-enable code in every board later. Just looked at your patches for omap3 and omap4: arch/arm/cpu/armv7/omap3/board.c | 8 ++++++++ arch/arm/cpu/armv7/omap4/board.c | 8 ++++++++ 2 files changed, 16 insertions(+), 0 deletions(-) Maybe there will be many many duplicated code like this, do you wish that? Jason diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 98519a9..de0e90d 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -390,3 +390,11 @@ void v7_outer_cache_disable(void) omap3_update_aux_cr(0, 0x2); } #endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index de4cc2a..6ea8a2e 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -139,3 +139,11 @@ void v7_outer_cache_disable(void) set_pl310_ctrl_reg(0); } #endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif