Patchwork [U-Boot] omap3:clock: configure GFX clock to 200MHz for AM/DM37x

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Submitter hvaibhav@ti.com
Date Aug. 1, 2011, 2:20 p.m.
Message ID <1312208458-25685-1-git-send-email-hvaibhav@ti.com>
Download mbox | patch
Permalink /patch/107750/
State Accepted
Commit f4dac3e16c1a08eb087e711a7e0ada3cf390d7ea
Headers show

Comments

hvaibhav@ti.com - Aug. 1, 2011, 2:20 p.m.
From: Vaibhav Hiremath <hvaibhav@ti.com>

AM/DM37x is another OMAP3 variant, where the GFX clock has been
boosted to 192MHz/200MHz. So fix the GFX_DIV value for this change.

HW Errata: Due to dependency of TV out clock of 54MHz, it is not
possible to configure GFX to 192MHz. So as per HW errats, the
recommended GFX clock is 200MHz (=CORE_CLK/2).

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 arch/arm/cpu/armv7/omap3/clock.c               |    2 +-
 arch/arm/include/asm/arch-omap3/clocks_omap3.h |    1 +
 2 files changed, 2 insertions(+), 1 deletions(-)

Patch

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 064fd3f..892d013 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -380,7 +380,7 @@  static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
 		/* L3 */
 		sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
 		/* GFX */
-		sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV);
+		sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV_36X);
 		/* RESET MGR */
 		sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
 		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
index 30ef690..c3c9ee3 100644
--- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h
+++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
@@ -39,6 +39,7 @@ 
 #define CORE_L4_DIV	2	/* 83MHz  : L4 */
 #define CORE_L3_DIV	2	/* 166MHz : L3 {DDR} */
 #define GFX_DIV		2	/* 83MHz  : CM_CLKSEL_GFX */
+#define GFX_DIV_36X	5	/* 200MHz : CM_CLKSEL_GFX */
 #define WKUP_RSM	2	/* 41.5MHz: CM_CLKSEL_WKUP */
 
 /* PER DPLL */