Patchwork [U-Boot] omap3:clock: check cpu_family before enabling clks for IVA & CAM

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Submitter hvaibhav@ti.com
Date Aug. 1, 2011, 2:20 p.m.
Message ID <1312208418-25626-1-git-send-email-hvaibhav@ti.com>
Download mbox | patch
Permalink /patch/107749/
State Accepted
Delegated to: Sandeep Paulraj
Headers show

Comments

hvaibhav@ti.com - Aug. 1, 2011, 2:20 p.m.
From: Vaibhav Hiremath <hvaibhav@ti.com>

In case of AM3517 and AM3505 (which is OMAP3 varients), IVA2 and
ISP-CAMERA modules have been removed. So add check for cpu_family before
enabling clocks for these modules, else this impacts subsequent
power consumption and system suspend/resume functionality.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
---
 arch/arm/cpu/armv7/omap3/clock.c |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)

--
1.6.2.4

Patch

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 2238c52..064fd3f 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -587,7 +587,8 @@  void prcm_init(void)

 		dpll3_init_34xx(sil_index, clk_index);
 		dpll4_init_34xx(sil_index, clk_index);
-		iva_init_34xx(sil_index, clk_index);
+		if (get_cpu_family() != CPU_AM35XX)
+			iva_init_34xx(sil_index, clk_index);
 		mpu_init_34xx(sil_index, clk_index);

 		/* Lock MPU DPLL to set frequency */
@@ -654,7 +655,9 @@  void per_clocks_enable(void)
 	/* Enable the ICLK for 32K Sync Timer as its used in udelay */
 	sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);

-	sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
+	if (get_cpu_family() != CPU_AM35XX)
+		sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
+
 	sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
 	sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
 	sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
@@ -662,8 +665,10 @@  void per_clocks_enable(void)
 	sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
 	sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
 	sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
-	sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
-	sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+	if (get_cpu_family() != CPU_AM35XX) {
+		sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
+		sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+	}
 	sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
 	sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);