diff mbox series

[U-Boot,v4,4/6] riscv: ax25: Andes specific cache shall only support in M-mode

Message ID 20190402075644.18089-5-uboot@andestech.com
State Accepted
Delegated to: Andes
Headers show
Series AE350 SMP support RISC-V | expand

Commit Message

Andes April 2, 2019, 7:56 a.m. UTC 
From: Rick Chen <rick@andestech.com>

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
 arch/riscv/cpu/ax25/Kconfig | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 68bd4e9..6b4b92e 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -14,6 +14,7 @@  if RISCV_NDS
 
 config RISCV_NDS_CACHE
 	bool "AndeStar V5 families specific cache support"
+	depends on RISCV_MMODE
 	help
 	  Provide Andes Technology AndeStar V5 families specific cache support.