From patchwork Fri Jul 29 09:11:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 107374 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C4014B6F64 for ; Fri, 29 Jul 2011 21:58:05 +1000 (EST) Received: (qmail 3456 invoked by alias); 29 Jul 2011 11:58:04 -0000 Received: (qmail 3447 invoked by uid 22791); 29 Jul 2011 11:58:03 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-gw0-f47.google.com (HELO mail-gw0-f47.google.com) (74.125.83.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 29 Jul 2011 11:57:49 +0000 Received: by gwb11 with SMTP id 11so2974747gwb.20 for ; Fri, 29 Jul 2011 04:57:48 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.249.6 with SMTP id w6mr674583wfh.413.1311930688780; Fri, 29 Jul 2011 02:11:28 -0700 (PDT) Received: by 10.143.34.2 with HTTP; Fri, 29 Jul 2011 02:11:28 -0700 (PDT) Date: Fri, 29 Jul 2011 11:11:28 +0200 Message-ID: Subject: PATCH, v2: PR target/47715: [x32] Use SImode for thread pointer From: Uros Bizjak To: "H.J. Lu" Cc: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! ABI specifies that TP is loaded in ptr_mode. Attached patch implements this requirement. 2011-07-29 Uros Bizjak * config/i386/i386.md (*load_tp_x32): New. (*load_tp_x32_zext): Ditto. (*add_tp_x32): Ditto. (*add_tp_x32_zext): Ditto. (*load_tp_): Disable for !TARGET_X32 targets. (*add_tp_): Ditto. * config/i386/i386.c (get_thread_pointer): Load thread pointer in ptr_mode and convert to Pmode if needed. Testing on x86_64-pc-linux-gnu in progress. H.J., please test this version on x32. Uros. Index: i386.md =================================================================== --- i386.md (revision 176915) +++ i386.md (working copy) @@ -12444,10 +12444,32 @@ (define_mode_attr tp_seg [(SI "gs") (DI "fs")]) ;; Load and add the thread base pointer from %:0. +(define_insn "*load_tp_x32" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(const_int 0)] UNSPEC_TP))] + "TARGET_X32" + "mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" + [(set_attr "type" "imov") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + +(define_insn "*load_tp_x32_zext" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (unspec:SI [(const_int 0)] UNSPEC_TP)))] + "TARGET_X32" + "mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" + [(set_attr "type" "imov") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + (define_insn "*load_tp_" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(const_int 0)] UNSPEC_TP))] - "" + "!TARGET_X32" "mov{}\t{%%:0, %0|%0, PTR :0}" [(set_attr "type" "imov") (set_attr "modrm" "0") @@ -12455,12 +12477,39 @@ (set_attr "memory" "load") (set_attr "imm_disp" "false")]) +(define_insn "*add_tp_x32" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP) + (match_operand:SI 1 "register_operand" "0"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_X32" + "add{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" + [(set_attr "type" "alu") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + +(define_insn "*add_tp_x32_zext" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP) + (match_operand:SI 1 "register_operand" "0")))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_X32" + "add{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" + [(set_attr "type" "alu") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + (define_insn "*add_tp_" [(set (match_operand:P 0 "register_operand" "=r") (plus:P (unspec:P [(const_int 0)] UNSPEC_TP) (match_operand:P 1 "register_operand" "0"))) (clobber (reg:CC FLAGS_REG))] - "" + "!TARGET_X32" "add{}\t{%%:0, %0|%0, PTR :0}" [(set_attr "type" "alu") (set_attr "modrm" "0") Index: i386.c =================================================================== --- i386.c (revision 176915) +++ i386.c (working copy) @@ -12118,17 +12118,15 @@ legitimize_pic_address (rtx orig, rtx re static rtx get_thread_pointer (bool to_reg) { - rtx tp, reg, insn; + rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP); - tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP); - if (!to_reg) - return tp; + if (GET_MODE (tp) != Pmode) + tp = convert_to_mode (Pmode, tp, 1); - reg = gen_reg_rtx (Pmode); - insn = gen_rtx_SET (VOIDmode, reg, tp); - insn = emit_insn (insn); + if (to_reg) + tp = copy_addr_to_reg (tp); - return reg; + return tp; } /* Construct the SYMBOL_REF for the tls_get_addr function. */