From patchwork Thu Jul 28 13:40:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 107368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 4C737B6F64 for ; Fri, 29 Jul 2011 21:33:00 +1000 (EST) Received: (qmail 29104 invoked by alias); 29 Jul 2011 11:32:58 -0000 Received: (qmail 29096 invoked by uid 22791); 29 Jul 2011 11:32:58 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-yx0-f175.google.com (HELO mail-yx0-f175.google.com) (209.85.213.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 29 Jul 2011 11:32:44 +0000 Received: by yxi19 with SMTP id 19so2487336yxi.20 for ; Fri, 29 Jul 2011 04:32:43 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.249.6 with SMTP id w6mr664303wfh.413.1311860417592; Thu, 28 Jul 2011 06:40:17 -0700 (PDT) Received: by 10.143.34.2 with HTTP; Thu, 28 Jul 2011 06:40:17 -0700 (PDT) In-Reply-To: References: <20110728031121.GA11273@intel.com> Date: Thu, 28 Jul 2011 15:40:17 +0200 Message-ID: Subject: Re: PATCH: PR target/47715: [x32] Use SImode for thread pointer From: Uros Bizjak To: "H.J. Lu" Cc: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Thu, Jul 28, 2011 at 3:24 PM, H.J. Lu wrote: >>>> In x32, thread pointer is 32bit and choice of segment register for the >>>> thread base ptr load should be based on TARGET_64BIT.  This patch >>>> implements it.  OK for trunk? >>> >>> -ENOTESTCASE. >>> >> >> There is no standalone testcase.  The symptom is in glibc build, I >> got >> >> CPP='/export/build/gnu/gcc-x32/release/usr/gcc-4.7.0-x32/bin/gcc -mx32 >>  -E -x c-header' >> /export/build/gnu/glibc-x32/build-x86_64-linux/elf/ld-linux-x32.so.2 >> --library-path /export/build/gnu/glibc-x32/build-x86_64-linux:/export/build/gnu/glibc-x32/build-x86_64-linux/math:/export/build/gnu/glibc-x32/build-x86_64-linux/elf:/export/build/gnu/glibc-x32/build-x86_64-linux/dlfcn:/export/build/gnu/glibc-x32/build-x86_64-linux/nss:/export/build/gnu/glibc-x32/build-x86_64-linux/nis:/export/build/gnu/glibc-x32/build-x86_64-linux/rt:/export/build/gnu/glibc-x32/build-x86_64-linux/resolv:/export/build/gnu/glibc-x32/build-x86_64-linux/crypt:/export/build/gnu/glibc-x32/build-x86_64-linux/nptl >> /export/build/gnu/glibc-x32/build-x86_64-linux/sunrpc/rpcgen -Y >> ../scripts -h rpcsvc/yppasswd.x -o >> /export/build/gnu/glibc-x32/build-x86_64-linux/sunrpc/rpcsvc/yppasswd.T >> make[5]: *** [/export/build/gnu/glibc-x32/build-x86_64-linux/sunrpc/xbootparam_prot.stmp] >> Segmentation fault >> make[5]: *** Waiting for unfinished jobs.... >> make[5]: *** [/export/build/gnu/glibc-x32/build-x86_64-linux/sunrpc/xrstat.stmp] >> Segmentation fault >> make[5]: *** [/export/build/gnu/glibc-x32/build-x86_64-linux/sunrpc/xyppasswd.stmp] >> Segmentation fault >> >> since thread pointer is 32bit in x32. >> > > If we load thread pointer (fs segment register) in x32 with 64bit > load, the upper 32bits are garbage. > We must load 32bit So, instead of huge complications with new mode iterator, just introduce two new patterns that will shadow existing ones for TARGET_X32. Like in attached (untested) patch. Uros. Index: i386.md =================================================================== --- i386.md (revision 176860) +++ i386.md (working copy) @@ -12442,6 +12442,17 @@ (define_mode_attr tp_seg [(SI "gs") (DI "fs")]) ;; Load and add the thread base pointer from %:0. +(define_insn "*load_tp_x32" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(const_int 0)] UNSPEC_TP))] + "TARGET_X32" + "mov{l}\t{%%:0, %k0|%k0, DWORD PTR :0}" + [(set_attr "type" "imov") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + (define_insn "*load_tp_" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(const_int 0)] UNSPEC_TP))] @@ -12453,6 +12464,19 @@ (set_attr "memory" "load") (set_attr "imm_disp" "false")]) +(define_insn "*add_tp_x32" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP) + (match_operand:DI 1 "register_operand" "0"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_X32" + "add{l}\t{%%:0, %k0|%k0, DWORD PTR :0}" + [(set_attr "type" "alu") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + (define_insn "*add_tp_" [(set (match_operand:P 0 "register_operand" "=r") (plus:P (unspec:P [(const_int 0)] UNSPEC_TP)