From patchwork Thu Jul 28 16:25:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: nagabhushana.netagunte@ti.com X-Patchwork-Id: 107274 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CDAF3B6F57 for ; Fri, 29 Jul 2011 02:26:13 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6153D281B6; Thu, 28 Jul 2011 18:26:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aU0DZNTBILFo; Thu, 28 Jul 2011 18:26:11 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7B83B281A7; Thu, 28 Jul 2011 18:25:56 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0C177280FE for ; Thu, 28 Jul 2011 18:25:53 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vELJyoPDPeRl for ; Thu, 28 Jul 2011 18:25:50 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 53F4A2809E for ; Thu, 28 Jul 2011 18:25:48 +0200 (CEST) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6SGPfk8018620 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 28 Jul 2011 11:25:44 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6SGPeKA029766 for ; Thu, 28 Jul 2011 21:55:41 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Thu, 28 Jul 2011 21:55:40 +0530 Received: from psplinux051.india.ti.com (psplinux051.india.ti.com [172.24.162.244]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6SGPdIY000127; Thu, 28 Jul 2011 21:55:40 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id p6SGPdPH019005; Thu, 28 Jul 2011 21:55:39 +0530 Received: (from x0144960@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id p6SGPcuR019002; Thu, 28 Jul 2011 21:55:38 +0530 From: To: Date: Thu, 28 Jul 2011 21:55:25 +0530 Message-ID: <1311870338-18950-1-git-send-email-nagabhushana.netagunte@ti.com> X-Mailer: git-send-email 1.6.2.4 MIME-Version: 1.0 Cc: Nagabhushana Netagunte , sudhakar.raj@ti.com, manjunath.hadli@ti.com Subject: [U-Boot] [PATCH] da850: add NOR boot mode support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Nagabhushana Netagunte Add an option to use NOR boot mode in configuration file and correspanding pin-mux support in board file. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Nagabhushana Netagunte --- board/davinci/da8xxevm/da850evm.c | 50 +++++++++++++++++++++++++++++++++++++ include/configs/da850evm.h | 21 ++++++++++++++- 2 files changed, 70 insertions(+), 1 deletions(-) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 73eaa48..a77e438 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -105,6 +105,54 @@ const struct pinmux_config nand_pins[] = { { pinmux(12), 1, 5 }, { pinmux(12), 1, 6 } }; +#elif defined(CONFIG_SYS_USE_NOR) +const struct pinmux_config nor_pins[] = { + { pinmux(5), 1, 6 }, + { pinmux(6), 1, 6 }, + { pinmux(7), 1, 0 }, + { pinmux(7), 1, 4 }, + { pinmux(7), 1, 5 }, + { pinmux(8), 1, 0 }, + { pinmux(8), 1, 1 }, + { pinmux(8), 1, 2 }, + { pinmux(8), 1, 3 }, + { pinmux(8), 1, 4 }, + { pinmux(8), 1, 5 }, + { pinmux(8), 1, 6 }, + { pinmux(8), 1, 7 }, + { pinmux(9), 1, 0 }, + { pinmux(9), 1, 1 }, + { pinmux(9), 1, 2 }, + { pinmux(9), 1, 3 }, + { pinmux(9), 1, 4 }, + { pinmux(9), 1, 5 }, + { pinmux(9), 1, 6 }, + { pinmux(9), 1, 7 }, + { pinmux(10), 1, 0 }, + { pinmux(10), 1, 1 }, + { pinmux(10), 1, 2 }, + { pinmux(10), 1, 3 }, + { pinmux(10), 1, 4 }, + { pinmux(10), 1, 5 }, + { pinmux(10), 1, 6 }, + { pinmux(10), 1, 7 }, + { pinmux(11), 1, 0 }, + { pinmux(11), 1, 1 }, + { pinmux(11), 1, 2 }, + { pinmux(11), 1, 3 }, + { pinmux(11), 1, 4 }, + { pinmux(11), 1, 5 }, + { pinmux(11), 1, 6 }, + { pinmux(11), 1, 7 }, + { pinmux(12), 1, 0 }, + { pinmux(12), 1, 1 }, + { pinmux(12), 1, 2 }, + { pinmux(12), 1, 3 }, + { pinmux(12), 1, 4 }, + { pinmux(12), 1, 5 }, + { pinmux(12), 1, 6 }, + { pinmux(12), 1, 7 } +}; #endif #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII @@ -122,6 +170,8 @@ static const struct pinmux_resource pinmuxes[] = { PINMUX_ITEM(i2c_pins), #ifdef CONFIG_NAND_DAVINCI PINMUX_ITEM(nand_pins), +#elif defined(CONFIG_USE_NOR) + PINMUX_ITEM(nor_pins), #endif }; diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index fdcc6e3..f0015e4 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -28,6 +28,8 @@ */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_USE_SPIFLASH +#undef CONFIG_USE_NAND +#undef CONFIG_SYS_USE_NOR /* * SoC Configuration @@ -129,6 +131,23 @@ #define CONFIG_NET_MULTI #endif +#ifdef CONFIG_SYS_USE_NOR +#define CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ +#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ +#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ + + 3) +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ +#endif + #ifdef CONFIG_USE_SPIFLASH #undef CONFIG_ENV_IS_IN_FLASH #undef CONFIG_ENV_IS_IN_NAND @@ -212,7 +231,7 @@ #endif #if !defined(CONFIG_USE_NAND) && \ - !defined(CONFIG_USE_NOR) && \ + !defined(CONFIG_SYS_USE_NOR) && \ !defined(CONFIG_USE_SPIFLASH) #define CONFIG_ENV_IS_NOWHERE #define CONFIG_SYS_NO_FLASH