From patchwork Mon Jul 25 23:00:00 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 106760 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 48AC4B70FF for ; Tue, 26 Jul 2011 09:00:23 +1000 (EST) Received: (qmail 28801 invoked by alias); 25 Jul 2011 23:00:20 -0000 Received: (qmail 28764 invoked by uid 22791); 25 Jul 2011 23:00:19 -0000 X-SWARE-Spam-Status: No, hits=-6.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 25 Jul 2011 23:00:01 +0000 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p6PN00AJ029626 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Mon, 25 Jul 2011 19:00:01 -0400 Received: from anchor.twiddle.net (vpn-227-66.phx2.redhat.com [10.3.227.66]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p6PN00wU031748 for ; Mon, 25 Jul 2011 19:00:00 -0400 Message-ID: <4E2DF570.6010402@redhat.com> Date: Mon, 25 Jul 2011 16:00:00 -0700 From: Richard Henderson User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:5.0) Gecko/20110707 Thunderbird/5.0 MIME-Version: 1.0 To: GCC Patches Subject: Fix debug/49841 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The ICE caught what it was supposed to catch. However, what the rs6000 port was intending to describe was the unconditional availability of R2 at a given offset after the conditional store. Approved by dje in the PR. r~ PR debug/49841 * config/rs6000/rs6000.c (rs6000_frame_related): Return the insn. (emit_frame_save): Likewise. (rs6000_emit_prologue): Move the FRAME_RELATED_EXPR from the save insn onto a dummy blockage insn after the join label. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 0d4e6d5..fa367fe 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -872,10 +872,7 @@ static bool rs6000_legitimate_address_p (enum machine_mode, rtx, bool); static bool rs6000_debug_legitimate_address_p (enum machine_mode, rtx, bool); static rtx rs6000_generate_compare (rtx, enum machine_mode); static void rs6000_emit_stack_tie (void); -static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); static bool spe_func_has_64bit_regs_p (void); -static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, - int, HOST_WIDE_INT); static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); static unsigned rs6000_hash_constant (rtx); static unsigned toc_hash_function (const void *); @@ -19317,7 +19314,7 @@ output_probe_stack_range (rtx reg1, rtx reg2) deduce these equivalences by itself so it wasn't necessary to hold its hand so much. */ -static void +static rtx rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, rtx reg2, rtx rreg) { @@ -19390,6 +19387,8 @@ rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, RTX_FRAME_RELATED_P (insn) = 1; add_reg_note (insn, REG_FRAME_RELATED_EXPR, real); + + return insn; } /* Returns an insn that has a vrsave set operation with the @@ -19454,7 +19453,7 @@ generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ -static void +static rtx emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, unsigned int regno, int offset, HOST_WIDE_INT total_size) { @@ -19492,7 +19491,7 @@ emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, insn = emit_move_insn (mem, reg); - rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); + return rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); } /* Emit an offset memory reference suitable for a frame store, while @@ -20288,6 +20287,7 @@ rs6000_emit_prologue (void) if (TARGET_AIX && crtl->calls_eh_return) { rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump; + rtx save_insn, join_insn, note; long toc_restore_insn; gcc_assert (frame_reg_rtx == frame_ptr_rtx @@ -20322,9 +20322,29 @@ rs6000_emit_prologue (void) JUMP_LABEL (jump) = toc_save_done; LABEL_NUSES (toc_save_done) += 1; - emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, TOC_REGNUM, - sp_offset + 5 * reg_size, info->total_size); + save_insn = emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, + TOC_REGNUM, sp_offset + 5 * reg_size, + info->total_size); + emit_label (toc_save_done); + + /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll + have a CFG that has different saves along different paths. + Move the note to a dummy blockage insn, which describes that + R2 is unconditionally saved after the label. */ + /* ??? An alternate representation might be a special insn pattern + containing both the branch and the store. That might let the + code that minimizes the number of DW_CFA_advance opcodes better + freedom in placing the annotations. */ + note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL); + gcc_assert (note); + remove_note (save_insn, note); + RTX_FRAME_RELATED_P (save_insn) = 0; + + join_insn = emit_insn (gen_blockage ()); + REG_NOTES (join_insn) = note; + RTX_FRAME_RELATED_P (join_insn) = 1; + if (using_static_chain_p) emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0)); }