Patchwork [U-Boot,V2,3/5] nand spl: add NAND Library to new SPL

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Submitter Simon Schwarz
Date July 25, 2011, 6:05 p.m.
Message ID <1311617138-17041-4-git-send-email-simonschwarzcor@gmail.com>
Download mbox | patch
Permalink /patch/106730/
State Superseded
Headers show

Comments

Simon Schwarz - July 25, 2011, 6:05 p.m.
Insert some NAND driver sources into NAND SPL library.

---
V1 changes:
CHG Default to HW ecc in SPL build
ADD nand_read_buf16 function, read buffer
ADD omap_dev_ready function, indicte if chip is ready

V2 changes:
DEL GPMC_WAIT0_PIN_ACTIVE define
CHG omap_dev_ready() renamed to  omap_spl_dev_ready(), does not use the
	GPMC_WAIT0_PIN_ACTIVE-define anymore
CHG ogpmc_read_buf16 renamed omap_spl_read_buf16
ADD omap_spl_read_buf, 8x buf read function
ADD CONFIG_SPL_POWER_SUPPORT and CONFIG_SPL_NAND_SUPPORT to SPL
CHG cosmetic
CHG nand_base and nand_bbt aren't needed for SPL anymore
CHG omap_nand_switch_ecc is not compiled for SPL
ADD entry for CONFIG_SPL_POWER_SUPPORT and CONFIG_SPL_NAND_SUPPORT to README.SPL

Transition from V1 to V2 also includes that this patch is now based on
	- the new SPL layout by Aneesh V and Daniel Schwierzeck
	- the OMAP4 SPL patches by Aneesh V

This Patch is related to "[U-Boot,4/5] devkit8000 nand_spl: Add SPL NAND support
to omap_gpmc driver"
(http://article.gmane.org/gmane.comp.boot-loaders.u-boot/102115) in V1

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
---
 doc/README.SPL               |    2 +
 drivers/mtd/nand/Makefile    |    6 +++-
 drivers/mtd/nand/omap_gpmc.c |   69 ++++++++++++++++++++++++++++++++++++++++++
 spl/Makefile                 |    2 +
 4 files changed, 78 insertions(+), 1 deletions(-)
Andreas Bießmann - July 26, 2011, 5:59 a.m.
Dear Simon,

Am 25.07.2011 um 20:05 schrieb Simon Schwarz:

> Insert some NAND driver sources into NAND SPL library.
> 
> ---
> V1 changes:
> CHG Default to HW ecc in SPL build
> ADD nand_read_buf16 function, read buffer
> ADD omap_dev_ready function, indicte if chip is ready
> 
> V2 changes:
> DEL GPMC_WAIT0_PIN_ACTIVE define
> CHG omap_dev_ready() renamed to  omap_spl_dev_ready(), does not use the
> 	GPMC_WAIT0_PIN_ACTIVE-define anymore
> CHG ogpmc_read_buf16 renamed omap_spl_read_buf16
> ADD omap_spl_read_buf, 8x buf read function
> ADD CONFIG_SPL_POWER_SUPPORT and CONFIG_SPL_NAND_SUPPORT to SPL
> CHG cosmetic
> CHG nand_base and nand_bbt aren't needed for SPL anymore
> CHG omap_nand_switch_ecc is not compiled for SPL
> ADD entry for CONFIG_SPL_POWER_SUPPORT and CONFIG_SPL_NAND_SUPPORT to README.SPL
> 
> Transition from V1 to V2 also includes that this patch is now based on
> 	- the new SPL layout by Aneesh V and Daniel Schwierzeck
> 	- the OMAP4 SPL patches by Aneesh V
> 
> This Patch is related to "[U-Boot,4/5] devkit8000 nand_spl: Add SPL NAND support
> to omap_gpmc driver"
> (http://article.gmane.org/gmane.comp.boot-loaders.u-boot/102115) in V1
> 
> Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
> ---
> doc/README.SPL               |    2 +
> drivers/mtd/nand/Makefile    |    6 +++-
> drivers/mtd/nand/omap_gpmc.c |   69 ++++++++++++++++++++++++++++++++++++++++++
> spl/Makefile                 |    2 +
> 4 files changed, 78 insertions(+), 1 deletions(-)

<snip>

> --- a/drivers/mtd/nand/omap_gpmc.c
> +++ b/drivers/mtd/nand/omap_gpmc.c
> @@ -61,6 +61,55 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
> 		writeb(cmd, this->IO_ADDR_W);
> }

<snip>

> @@ -224,6 +273,8 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
> 	}
> }
> 
> +

This single line is unnecessary.

> +#ifndef CONFIG_SPL_BUILD
> /*
>  * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
>  * The default is to come up on s/w ecc
> @@ -280,6 +331,7 @@ void omap_nand_switch_ecc(int32_t hardware)
> 

regards

Andreas Bießmann
Simon Schwarz - July 26, 2011, 8:47 a.m.
Dear Andreas,

On 07/26/2011 07:59 AM, Andreas Bießmann wrote:
> Dear Simon,
>
> Am 25.07.2011 um 20:05 schrieb Simon Schwarz:
>
>> Insert some NAND driver sources into NAND SPL library.
>>
>> ---
>> V1 changes:
>> CHG Default to HW ecc in SPL build
>> ADD nand_read_buf16 function, read buffer
>> ADD omap_dev_ready function, indicte if chip is ready
>>
>> V2 changes:
>> DEL GPMC_WAIT0_PIN_ACTIVE define
>> CHG omap_dev_ready() renamed to  omap_spl_dev_ready(), does not use the
>> 	GPMC_WAIT0_PIN_ACTIVE-define anymore
>> CHG ogpmc_read_buf16 renamed omap_spl_read_buf16
>> ADD omap_spl_read_buf, 8x buf read function
>> ADD CONFIG_SPL_POWER_SUPPORT and CONFIG_SPL_NAND_SUPPORT to SPL
>> CHG cosmetic
>> CHG nand_base and nand_bbt aren't needed for SPL anymore
>> CHG omap_nand_switch_ecc is not compiled for SPL
>> ADD entry for CONFIG_SPL_POWER_SUPPORT and CONFIG_SPL_NAND_SUPPORT to README.SPL
>>
>> Transition from V1 to V2 also includes that this patch is now based on
>> 	- the new SPL layout by Aneesh V and Daniel Schwierzeck
>> 	- the OMAP4 SPL patches by Aneesh V
>>
>> This Patch is related to "[U-Boot,4/5] devkit8000 nand_spl: Add SPL NAND support
>> to omap_gpmc driver"
>> (http://article.gmane.org/gmane.comp.boot-loaders.u-boot/102115) in V1
>>
>> Signed-off-by: Simon Schwarz<simonschwarzcor@gmail.com>
>> ---
>> doc/README.SPL               |    2 +
>> drivers/mtd/nand/Makefile    |    6 +++-
>> drivers/mtd/nand/omap_gpmc.c |   69 ++++++++++++++++++++++++++++++++++++++++++
>> spl/Makefile                 |    2 +
>> 4 files changed, 78 insertions(+), 1 deletions(-)
>
> <snip>
>
>> --- a/drivers/mtd/nand/omap_gpmc.c
>> +++ b/drivers/mtd/nand/omap_gpmc.c
>> @@ -61,6 +61,55 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
>> 		writeb(cmd, this->IO_ADDR_W);
>> }
>
> <snip>
>
>> @@ -224,6 +273,8 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
>> 	}
>> }
>>
>> +
>
> This single line is unnecessary.
deleted...
>
>> +#ifndef CONFIG_SPL_BUILD
>> /*
>>   * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
>>   * The default is to come up on s/w ecc
>> @@ -280,6 +331,7 @@ void omap_nand_switch_ecc(int32_t hardware)
>>
>
> regards
>
> Andreas Bießmann

regards
Simon

Patch

diff --git a/doc/README.SPL b/doc/README.SPL
index ce8e19f..2987f43 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -60,3 +60,5 @@  CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
 CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
 CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
 CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
+CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
+CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8b598f6..cdc9a14 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -26,12 +26,16 @@  include $(TOPDIR)/config.mk
 LIB	:= $(obj)libnand.o
 
 ifdef CONFIG_CMD_NAND
+ifdef CONFIG_SPL_BUILD
+COBJS-y += nand_spl.o
+else
 COBJS-y += nand.o
 COBJS-y += nand_base.o
 COBJS-y += nand_bbt.o
-COBJS-y += nand_ecc.o
 COBJS-y += nand_ids.o
 COBJS-y += nand_util.o
+endif
+COBJS-y += nand_ecc.o
 
 COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
 COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 99b9cef..ee4d13e 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -61,6 +61,55 @@  static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 		writeb(cmd, this->IO_ADDR_W);
 }
 
+#ifdef CONFIG_SPL_BUILD
+/* Check wait pin as dev ready indicator */
+int omap_spl_dev_ready(struct mtd_info *mtd)
+{
+	return gpmc_cfg->status & (1 << 8);
+}
+
+/*
+ * omap_spl_read_buf16 - [DEFAULT] read chip data into buffer
+ * @mtd:    MTD device structure
+ * @buf:    buffer to store date
+ * @len:    number of bytes to read
+ *
+ * Default read function for 16bit buswith
+ *
+ * This function is based on nand_read_buf16 from nand_base.c. This version
+ * reads 32bit not 16bit although the bus only has 16bit.
+ */
+static void omap_spl_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+	u32 *p = (u32 *) buf;
+	len >>= 2;
+
+	for (i = 0; i < len; i++)
+		p[i] = readl(chip->IO_ADDR_R);
+}
+
+/*
+ * omap_spl_read_buf - [DEFAULT] read chip data into buffer
+ * @mtd:    MTD device structure
+ * @buf:    buffer to store date
+ * @len:    number of bytes to read
+ *
+ * Default read function for 8bit buswith
+ *
+ * This is the same function as this from nand_base.c nand_read_buf
+ */
+static void omap_spl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+
+	for (i = 0; i < len; i++)
+		buf[i] = readb(chip->IO_ADDR_R);
+}
+#endif
+
 /*
  * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
  *                   GPMC controller
@@ -224,6 +273,8 @@  static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 	}
 }
 
+
+#ifndef CONFIG_SPL_BUILD
 /*
  * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
  * The default is to come up on s/w ecc
@@ -280,6 +331,7 @@  void omap_nand_switch_ecc(int32_t hardware)
 
 	nand->options &= ~NAND_OWN_BUFFERS;
 }
+#endif /* CONFIG_SPL_BUILD */
 
 /*
  * Board-specific NAND initialization. The following members of the
@@ -338,7 +390,24 @@  int board_nand_init(struct nand_chip *nand)
 
 	nand->chip_delay = 100;
 	/* Default ECC mode */
+#ifndef CONFIG_SPL_BUILD
 	nand->ecc.mode = NAND_ECC_SOFT;
+#else
+	nand->ecc.mode = NAND_ECC_HW;
+	nand->ecc.layout = &hw_nand_oob;
+	nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
+	nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+	nand->ecc.hwctl = omap_enable_hwecc;
+	nand->ecc.correct = omap_correct_data;
+	nand->ecc.calculate = omap_calculate_ecc;
+	omap_hwecc_init(nand);
+
+	if (nand->options & NAND_BUSWIDTH_16)
+		nand->read_buf = omap_spl_read_buf16;
+	else
+		nand->read_buf = omap_spl_read_buf;
+	nand->dev_ready = omap_spl_dev_ready;
+#endif
 
 	return 0;
 }
diff --git a/spl/Makefile b/spl/Makefile
index 87f13f6..0c0d3c4 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -46,6 +46,8 @@  LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
 LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
 LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
 LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
+LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
+LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
 
 ifeq ($(SOC),omap3)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o