From patchwork Sun Jul 24 17:10:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 106543 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 871D2B6F82 for ; Mon, 25 Jul 2011 03:47:30 +1000 (EST) Received: from localhost ([::1]:48061 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ql2Ei-000452-3V for incoming@patchwork.ozlabs.org; Sun, 24 Jul 2011 13:13:04 -0400 Received: from eggs.gnu.org ([140.186.70.92]:57411) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ql2E3-0002M7-0K for qemu-devel@nongnu.org; Sun, 24 Jul 2011 13:12:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ql2E2-0005G1-0k for qemu-devel@nongnu.org; Sun, 24 Jul 2011 13:12:22 -0400 Received: from mail-fx0-f47.google.com ([209.85.161.47]:56785) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ql2E1-0004u6-SM for qemu-devel@nongnu.org; Sun, 24 Jul 2011 13:12:21 -0400 Received: by mail-fx0-f47.google.com with SMTP id 11so8353846fxg.34 for ; Sun, 24 Jul 2011 10:12:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=18659mbZ86LwECdoKKte8ZO3PZvf12R9IR3e41JOfBg=; b=gC0E+ICuxfYCG9zUFhwXlrOM6aT+4YoYYLSJh78m2UzpcLPVMU9kSZd2IXFUSbgKAF 1f02T0W+Qwgf4Vn47L+impbdjnz/DH0RXa+bfu0B+VO6pOg+bPhU1+VJXTC6JbOJ7SB2 Ov/EMX0TiobfA5MFM5VPZs6GpHH3+Mw3FJyQI= Received: by 10.204.136.91 with SMTP id q27mr608290bkt.222.1311527541423; Sun, 24 Jul 2011 10:12:21 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id b10sm1071454bka.48.2011.07.24.10.12.18 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 24 Jul 2011 10:12:20 -0700 (PDT) Received: by octofox.metropolis (sSMTP sendmail emulation); Sun, 24 Jul 2011 21:12:17 +0400 From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 24 Jul 2011 21:10:45 +0400 Message-Id: <1311527469-12963-8-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1311527469-12963-1-git-send-email-jcmvbkbc@gmail.com> References: <1311527469-12963-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.161.47 Cc: jcmvbkbc@gmail.com Subject: [Qemu-devel] [PATCH v2 07/31] target-xtensa: implement conditional jumps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org - BZ (comparison to zero); - BI0 (comparison to signed immediate); - BI1 (comparison to unsigned immediate); - B (two registers comparison, bit sets comparison); - BEQZ.N/BNEZ.N (narrow comparison to zero). Signed-off-by: Max Filippov --- target-xtensa/translate.c | 164 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 164 insertions(+), 0 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index dcbc0ae..c6ebb3d 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -121,6 +121,25 @@ static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) tcg_temp_free(tmp); } +static void gen_brcond(DisasContext *dc, TCGCond cond, + TCGv_i32 t0, TCGv_i32 t1, uint32_t offset) +{ + int label = gen_new_label(); + + tcg_gen_brcond_i32(cond, t0, t1, label); + gen_jumpi(dc, dc->next_pc, 0); + gen_set_label(label); + gen_jumpi(dc, dc->pc + offset, 1); +} + +static void gen_brcondi(DisasContext *dc, TCGCond cond, + TCGv_i32 t0, uint32_t t1, uint32_t offset) +{ + TCGv_i32 tmp = tcg_const_i32(t1); + gen_brcond(dc, cond, t0, tmp, offset); + tcg_temp_free(tmp); +} + static void disas_xtensa_insn(DisasContext *dc) { #define HAS_OPTION(opt) do { \ @@ -202,6 +221,14 @@ static void disas_xtensa_insn(DisasContext *dc) uint8_t _b1 = ldub_code(dc->pc + 1); uint8_t _b2 = ldub_code(dc->pc + 2); + static const uint32_t B4CONST[] = { + 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 + }; + + static const uint32_t B4CONSTU[] = { + 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 + }; + if (_OP0 >= 8) { dc->next_pc = dc->pc + 2; HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); @@ -395,10 +422,143 @@ static void disas_xtensa_insn(DisasContext *dc) gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0); break; + case 1: /*BZ*/ + { + static const TCGCond cond[] = { + TCG_COND_EQ, /*BEQZ*/ + TCG_COND_NE, /*BNEZ*/ + TCG_COND_LT, /*BLTZ*/ + TCG_COND_GE, /*BGEZ*/ + }; + + gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0, + 4 + BRI12_IMM12_SE); + } + break; + + case 2: /*BI0*/ + { + static const TCGCond cond[] = { + TCG_COND_EQ, /*BEQI*/ + TCG_COND_NE, /*BNEI*/ + TCG_COND_LT, /*BLTI*/ + TCG_COND_GE, /*BGEI*/ + }; + + gen_brcondi(dc, cond[BRI8_M & 3], + cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE); + } + break; + + case 3: /*BI1*/ + switch (BRI8_M) { + case 0: /*ENTRYw*/ + HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + break; + + case 1: /*B1*/ + switch (BRI8_R) { + case 0: /*BFp*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + break; + + case 1: /*BTp*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + break; + + case 8: /*LOOP*/ + break; + + case 9: /*LOOPNEZ*/ + break; + + case 10: /*LOOPGTZ*/ + break; + + default: /*reserved*/ + break; + + } + break; + + case 2: /*BLTUI*/ + case 3: /*BGEUI*/ + gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU, + cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE); + break; + } + break; + } break; case 7: /*B*/ + { + TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ; + + switch (RRI8_R & 7) { + case 0: /*BNONE*/ /*BANY*/ + { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); + gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); + tcg_temp_free(tmp); + } + break; + + case 1: /*BEQ*/ /*BNE*/ + case 2: /*BLT*/ /*BGE*/ + case 3: /*BLTU*/ /*BGEU*/ + { + static const TCGCond cond[] = { + [1] = TCG_COND_EQ, + [2] = TCG_COND_LT, + [3] = TCG_COND_LTU, + [9] = TCG_COND_NE, + [10] = TCG_COND_GE, + [11] = TCG_COND_GEU, + }; + gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T], + 4 + RRI8_IMM8_SE); + } + break; + + case 4: /*BALL*/ /*BNALL*/ + { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); + gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T], + 4 + RRI8_IMM8_SE); + tcg_temp_free(tmp); + } + break; + + case 5: /*BBC*/ /*BBS*/ + { + TCGv_i32 bit = tcg_const_i32(1); + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f); + tcg_gen_shl_i32(bit, bit, tmp); + tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit); + gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); + tcg_temp_free(tmp); + tcg_temp_free(bit); + } + break; + + case 6: /*BBCI*/ /*BBSI*/ + case 7: + { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, cpu_R[RRI8_S], + 1 << (((RRI8_R & 1) << 4) | RRI8_T)); + gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); + tcg_temp_free(tmp); + } + break; + + } + } break; #define gen_narrow_load_store(type) do { \ @@ -431,6 +591,10 @@ static void disas_xtensa_insn(DisasContext *dc) RRRN_R | (RRRN_T << 4) | ((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ + TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ; + + gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0, + 4 + (RRRN_R | ((RRRN_T & 3) << 4))); } break;