From patchwork Sun Jul 24 17:10:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 106532 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 51B94B6F83 for ; Mon, 25 Jul 2011 03:13:56 +1000 (EST) Received: from localhost ([::1]:51016 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ql2FU-0005iW-La for incoming@patchwork.ozlabs.org; Sun, 24 Jul 2011 13:13:52 -0400 Received: from eggs.gnu.org ([140.186.70.92]:57649) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ql2FJ-0005XH-7d for qemu-devel@nongnu.org; Sun, 24 Jul 2011 13:13:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ql2F3-0005M3-VP for qemu-devel@nongnu.org; Sun, 24 Jul 2011 13:13:27 -0400 Received: from mail-fx0-f47.google.com ([209.85.161.47]:58230) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ql2F3-0005Lw-Ix for qemu-devel@nongnu.org; Sun, 24 Jul 2011 13:13:25 -0400 Received: by fxg11 with SMTP id 11so8355253fxg.34 for ; Sun, 24 Jul 2011 10:13:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=8Ww119tn6yRE2fxwVtbaSr1EnlvHPT/IzTKSW8WZ174=; b=sg6hCER0cd/WO4PkVe9hxDaWpITPt0Hfac83DxcJRx/88vHnzjS28VAZjV9pkPTxb8 R1dh4QHWZlOVlWUPpePt/8qQk2ePcHLSjbFjUWBBUD7lOCC+2e2/Er4FbxD3oc+3k4kO tzJK5ijrVpCMGGc3IVtz9+cEqsKVMOI4Y+3hk= Received: by 10.204.7.205 with SMTP id e13mr995120bke.36.1311527601743; Sun, 24 Jul 2011 10:13:21 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id x19sm1072268bkt.9.2011.07.24.10.13.19 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 24 Jul 2011 10:13:21 -0700 (PDT) Received: by octofox.metropolis (sSMTP sendmail emulation); Sun, 24 Jul 2011 21:13:17 +0400 From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 24 Jul 2011 21:10:59 +0400 Message-Id: <1311527469-12963-22-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1311527469-12963-1-git-send-email-jcmvbkbc@gmail.com> References: <1311527469-12963-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.161.47 Cc: jcmvbkbc@gmail.com Subject: [Qemu-devel] [PATCH v2 21/31] target-xtensa: implement extended L32R X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org See ISA, 4.3.3 for details. TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR. Signed-off-by: Max Filippov --- v1 -> v2 changes: - do not encode LITBASE value into TB; --- target-xtensa/cpu.h | 6 ++++++ target-xtensa/helper.c | 1 + target-xtensa/translate.c | 37 +++++++++++++++++++++++++++++++++---- 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 787d306..850b7e4 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -110,6 +110,7 @@ enum { LEND = 1, LCOUNT = 2, SAR = 3, + LITBASE = 5, SCOMPARE1 = 12, WINDOW_BASE = 72, WINDOW_START = 73, @@ -274,6 +275,7 @@ static inline int cpu_mmu_index(CPUState *env) #define XTENSA_TBFLAG_RING_MASK 0x3 #define XTENSA_TBFLAG_EXCM 0x4 +#define XTENSA_TBFLAG_LITBASE 0x8 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -285,6 +287,10 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, if (env->sregs[PS] & PS_EXCM) { *flags |= XTENSA_TBFLAG_EXCM; } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |= XTENSA_TBFLAG_LITBASE; + } } #include "cpu-all.h" diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 3f8e944..84fe9e2 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -38,6 +38,7 @@ void cpu_reset(CPUXtensaState *env) { env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET]; + env->sregs[LITBASE] &= ~1; env->sregs[PS] = 0x1f; } diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index f2d22e7..889c9b2 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -49,6 +49,7 @@ typedef struct DisasContext { int ring; uint32_t lbeg; uint32_t lend; + TCGv_i32 litbase; int is_jmp; int singlestep_enabled; @@ -71,6 +72,7 @@ static const char * const sregnames[256] = { [LEND] = "LEND", [LCOUNT] = "LCOUNT", [SAR] = "SAR", + [LITBASE] = "LITBASE", [SCOMPARE1] = "SCOMPARE1", [WINDOW_BASE] = "WINDOW_BASE", [WINDOW_START] = "WINDOW_START", @@ -132,6 +134,21 @@ static inline bool option_enabled(DisasContext *dc, int opt) return xtensa_option_enabled(dc->config, opt); } +static void init_litbase(DisasContext *dc) +{ + if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { + dc->litbase = tcg_temp_local_new_i32(); + tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000); + } +} + +static void reset_litbase(DisasContext *dc) +{ + if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { + tcg_temp_free(dc->litbase); + } +} + static void init_sar_tracker(DisasContext *dc) { dc->sar_5bit = false; @@ -332,6 +349,13 @@ static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) dc->sar_m32_5bit = false; } +static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) +{ + tcg_gen_mov_i32(cpu_SR[sr], s); + /* This can change tb->flags, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); +} + static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) { gen_helper_wsr_windowbase(v); @@ -357,6 +381,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) [LBEG] = gen_wsr_lbeg, [LEND] = gen_wsr_lend, [SAR] = gen_wsr_sar, + [LITBASE] = gen_wsr_litbase, [WINDOW_BASE] = gen_wsr_windowbase, [PS] = gen_wsr_ps, }; @@ -1281,11 +1306,13 @@ static void disas_xtensa_insn(DisasContext *dc) case 1: /*L32R*/ { TCGv_i32 tmp = tcg_const_i32( - (0xfffc0000 | (RI16_IMM16 << 2)) + - ((dc->pc + 3) & ~3)); - - /* no ext L32R */ + ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? + 0 : ((dc->pc + 3) & ~3)) + + (0xfffc0000 | (RI16_IMM16 << 2))); + if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { + tcg_gen_add_i32(tmp, tmp, dc->litbase); + } tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring); tcg_temp_free(tmp); } @@ -1817,6 +1844,7 @@ static void gen_intermediate_code_internal( dc.lend = env->sregs[LEND]; dc.is_jmp = DISAS_NEXT; + init_litbase(&dc); init_sar_tracker(&dc); gen_icount_start(); @@ -1859,6 +1887,7 @@ static void gen_intermediate_code_internal( dc.pc < next_page_start && gen_opc_ptr < gen_opc_end); + reset_litbase(&dc); reset_sar_tracker(&dc); if (dc.is_jmp == DISAS_NEXT) {