diff --git a/gcc/ChangeLog.x32 b/gcc/ChangeLog.x32
index a4b34b9..5c2c673 100644
--- a/gcc/ChangeLog.x32
+++ b/gcc/ChangeLog.x32
@@ -1,3 +1,23 @@
+2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.md (general_operand): Replace
+	x32_general_operand with si_general_operand.
+	(general_szext_operand): Likewise.
+	(addsi_1_zext): Likewise.
+	(*addsi_2_zext): Likewise.
+	(*subsi_1_zext): Likewise.
+	(*subsi_2_zext): Likewise.
+	(*subsi_3_zext): Likewise.
+	(*addsi3_carry_zext): Likewise.
+	(*subsi3_carry_zext): Likewise.
+	(*andsi_1): Likewise.
+	(*andsi_1_zext): Likewise.
+	(*andsi_2_zext): Likewise.
+
+	* config/i386/predicates.md (x32_general_operand): Renamed to
+	...
+	(si_general_operand): This.
+
 2011-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/i386/i386.c (ix86_option_override_internal): Disallow
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 09ea1d4..c834bad 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -879,7 +879,7 @@
 (define_mode_attr general_operand
 	[(QI "general_operand")
 	 (HI "general_operand")
-	 (SI "x32_general_operand")
+	 (SI "si_general_operand")
 	 (DI "x86_64_general_operand")
 	 (TI "x86_64_general_operand")])
 
@@ -887,7 +887,7 @@
 (define_mode_attr general_szext_operand
 	[(QI "general_operand")
 	 (HI "general_operand")
-	 (SI "x32_general_operand")
+	 (SI "si_general_operand")
 	 (DI "x86_64_szext_general_operand")])
 
 ;; Immediate operand predicate for integer modes.
@@ -5531,7 +5531,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r,r,r")
 	(zero_extend:DI
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r,r")
-		   (match_operand:SI 2 "x32_general_operand" "rmYe,0,lYl"))))
+		   (match_operand:SI 2 "si_general_operand" "rmYe,0,lYl"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
 {
@@ -5920,7 +5920,7 @@
   [(set (reg FLAGS_REG)
 	(compare
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-		   (match_operand:SI 2 "x32_general_operand" "rmYe"))
+		   (match_operand:SI 2 "si_general_operand" "rmYe"))
 	  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
@@ -6500,7 +6500,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
 	  (minus:SI (match_operand:SI 1 "register_operand" "0")
-		    (match_operand:SI 2 "x32_general_operand" "rmYe"))))
+		    (match_operand:SI 2 "si_general_operand" "rmYe"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sub{l}\t{%2, %k0|%k0, %2}"
@@ -6537,7 +6537,7 @@
   [(set (reg FLAGS_REG)
 	(compare
 	  (minus:SI (match_operand:SI 1 "register_operand" "0")
-		    (match_operand:SI 2 "x32_general_operand" "rmYe"))
+		    (match_operand:SI 2 "si_general_operand" "rmYe"))
 	  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
@@ -6564,7 +6564,7 @@
 (define_insn "*subsi_3_zext"
   [(set (reg FLAGS_REG)
 	(compare (match_operand:SI 1 "register_operand" "0")
-		 (match_operand:SI 2 "x32_general_operand" "rmYe")))
+		 (match_operand:SI 2 "si_general_operand" "rmYe")))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
 	  (minus:SI (match_dup 1)
@@ -6611,7 +6611,7 @@
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
 		   (plus:SI (match_operator 3 "ix86_carry_flag_operator"
 			     [(reg FLAGS_REG) (const_int 0)])
-			    (match_operand:SI 2 "x32_general_operand" "rmYe")))))
+			    (match_operand:SI 2 "si_general_operand" "rmYe")))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
   "adc{l}\t{%2, %k0|%k0, %2}"
@@ -6626,7 +6626,7 @@
 	  (minus:SI (match_operand:SI 1 "register_operand" "0")
 		    (plus:SI (match_operator 3 "ix86_carry_flag_operator"
 			      [(reg FLAGS_REG) (const_int 0)])
-			     (match_operand:SI 2 "x32_general_operand" "rmYe")))))
+			     (match_operand:SI 2 "si_general_operand" "rmYe")))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sbb{l}\t{%2, %k0|%k0, %2}"
@@ -7749,7 +7749,7 @@
 (define_insn "*andsi_1"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
 	(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
-		(match_operand:SI 2 "x32_general_operand" "rYe,rm,L")))
+		(match_operand:SI 2 "si_general_operand" "rYe,rm,L")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (AND, SImode, operands)"
 {
@@ -7796,7 +7796,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
 	  (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-		  (match_operand:SI 2 "x32_general_operand" "rmYe"))))
+		  (match_operand:SI 2 "si_general_operand" "rmYe"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
   "and{l}\t{%2, %k0|%k0, %2}"
@@ -7959,7 +7959,7 @@
   [(set (reg FLAGS_REG)
 	(compare (and:SI
 		  (match_operand:SI 1 "nonimmediate_operand" "%0")
-		  (match_operand:SI 2 "x32_general_operand" "rmYe"))
+		  (match_operand:SI 2 "si_general_operand" "rmYe"))
 		 (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 8b87753..56ce0a6 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1206,8 +1206,8 @@
   return !TARGET_X32 || !pic_32bit_operand (op, mode);
 })
 
-;; Return nonzero if OP is general operand representable on x32.
-(define_predicate "x32_general_operand"
+;; Test for a valid general operand for SImode.
+(define_predicate "si_general_operand"
   (if_then_else (and (match_test "TARGET_X32")
 		     (match_test "flag_pic"))
     (match_operand 0 "x86_64_general_operand")
