[U-Boot,RFC,2/2] board: ti: am654: select SYS_ARCH_IS_COHERENT for arm64
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Message ID 20190325172151.10638-3-vigneshr@ti.com
State RFC
Delegated to: Tom Rini
Headers show
Series
  • Add Kconfig to disable cache ops
Related show

Commit Message

Vignesh Raghavendra March 25, 2019, 5:21 p.m. UTC
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_ARCH_IS_COHERENT to avoid cache operations in A53 SPL/U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 board/ti/am65x/Kconfig | 1 +
 1 file changed, 1 insertion(+)

Patch
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diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index d4b36dbb42f3..2c4a02834fc2 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -11,6 +11,7 @@  config TARGET_AM654_A53_EVM
 	bool "TI K3 based AM654 EVM running on A53"
 	select ARM64
 	select SOC_K3_AM6
+	select SYS_ARCH_IS_COHERENT
 
 config TARGET_AM654_R5_EVM
 	bool "TI K3 based AM654 EVM running on R5"