From patchwork Sat Jul 23 02:20:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsuneo Saito X-Patchwork-Id: 106407 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 08513B6F6F for ; Sat, 23 Jul 2011 12:21:14 +1000 (EST) Received: from localhost ([::1]:42876 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QkRq2-0004ON-Iz for incoming@patchwork.ozlabs.org; Fri, 22 Jul 2011 22:21:10 -0400 Received: from eggs.gnu.org ([140.186.70.92]:55908) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QkRpr-0004Lz-FI for qemu-devel@nongnu.org; Fri, 22 Jul 2011 22:21:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QkRpq-0004RS-Gn for qemu-devel@nongnu.org; Fri, 22 Jul 2011 22:20:59 -0400 Received: from mail-pz0-f43.google.com ([209.85.210.43]:58490) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QkRpq-0004RE-8Y for qemu-devel@nongnu.org; Fri, 22 Jul 2011 22:20:58 -0400 Received: by pzk1 with SMTP id 1so4828422pzk.30 for ; Fri, 22 Jul 2011 19:20:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=FwrH1M96b1YwfDDY3Rf8+hYsA/ryFYYDuAhkz5tICNw=; b=YQmE1vLyVmhA1LPSyyiYctvWGJM5OTbuTI0rsE0MJ9axQz1cNvRbD1ohPpWSDRX86e PoezLzr/KyXSHuPeAY73HlnQGReg8oyXcCymuoo3DOmPYKlrR28CKOHySwIiWP5iKCNS GomFsDh4EdV4jxvHyjdhF9TJzINEeyKtuTTBU= Received: by 10.68.10.202 with SMTP id k10mr3131839pbb.511.1311387657602; Fri, 22 Jul 2011 19:20:57 -0700 (PDT) Received: from localhost.localdomain (tetkyo149119.tkyo.te.ftth2.ppp.infoweb.ne.jp [202.219.195.119]) by mx.google.com with ESMTPS id q2sm2268973pbj.19.2011.07.22.19.20.56 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 22 Jul 2011 19:20:57 -0700 (PDT) From: Tsuneo Saito To: qemu-devel@nongnu.org Date: Sat, 23 Jul 2011 11:20:06 +0900 Message-Id: <1311387607-56720-2-git-send-email-tsnsaito@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1311387607-56720-1-git-send-email-tsnsaito@gmail.com> References: <1311387607-56720-1-git-send-email-tsnsaito@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.43 Cc: Tsuneo Saito Subject: [Qemu-devel] [PATCH 1/2] SPARC64: fix fnor* and fnand* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix the problem that result values are not assigned to the destination registers. Signed-off-by: Tsuneo Saito --- target-sparc/translate.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 15967c5..f68b3bc 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3980,14 +3980,15 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x062: /* VIS I fnor */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + tcg_gen_nor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], cpu_fpr[DFPREG(rs2)]); - tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + tcg_gen_nor_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], cpu_fpr[DFPREG(rs2) + 1]); break; case 0x063: /* VIS I fnors */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); + tcg_gen_nor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x064: /* VIS I fandnot2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4047,14 +4048,15 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x06e: /* VIS I fnand */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + tcg_gen_nand_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], cpu_fpr[DFPREG(rs2)]); - tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + tcg_gen_nand_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], cpu_fpr[DFPREG(rs2) + 1]); break; case 0x06f: /* VIS I fnands */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); + tcg_gen_nand_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x070: /* VIS I fand */ CHECK_FPU_FEATURE(dc, VIS1);