From patchwork Sun Mar 24 10:08:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiner Kallweit X-Patchwork-Id: 1063035 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pjbbYV2O"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44RtS23c1Pz9sSR for ; Sun, 24 Mar 2019 21:10:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728152AbfCXKKJ (ORCPT ); Sun, 24 Mar 2019 06:10:09 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:33419 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726160AbfCXKKI (ORCPT ); Sun, 24 Mar 2019 06:10:08 -0400 Received: by mail-wr1-f65.google.com with SMTP id q1so6884746wrp.0 for ; Sun, 24 Mar 2019 03:10:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:from:to:cc:references:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=dh0eGjsWZr93rloDe5Z0YufGXGB6udogFHumqDclilg=; b=pjbbYV2OdVHttRHWK4sUtNF6vRa1Ow+P8WU3Tx3ngLUKh8fz7oSR0IWOfk3yPjmDwS N0iVHghgVVklSkVilbKhpJU3IdPO3jWqjY02hv1p+vO/9wVffrP/iZXYKZjiPvV0XXPr xRp63r1Y/GEQYEhqPNkcPM9xV9CjoYRKzHiGSIL4gpAKEbPlcU/pj2jB3ODf1kOmOsYc 6yv7VNLb7T3s6SCFivAWEwpf7Wv6hqo+QRJxHHoc+14p5+9AcaoZW2y+D9aV7XVhM45L dl2KiSghu9tLmyNfbAvHC/ZMn6yFxfd7NpP0HdOb2L4i8gavs9SpLZ4NIGXqjGXqG5Y6 i/gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:references:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=dh0eGjsWZr93rloDe5Z0YufGXGB6udogFHumqDclilg=; b=arXawnyibwWoNmvwfLzmh3RE+YFjjdMBnFDmhgPoYSEUN6cr8mwaX5P+PnYbT6pfKZ +dYssCVXQw4PSFGdbmX1hUpBl741TKpXaL+exbYjh5WiYwvcshxD58CZ4axTTaTuwXkl 8OCG4wKkNPmkEmbCrC2fI2Mvm/ElIp/5Gi06blEH0fn/JzJlC6/G5ypf7hd7tDzdv2Su Cdlciw3VLqbfyb8Qy1BbIQ0L2drkOfJgoFzLBUcXEG90Sb+KMGiVBiQT2lXSk2vcxBoj vG9t5L6VOpx8bbWDvksNl0ZV1HK01QKS8ARN+jqE3HB9zKabmTuGg8nyB98ao5BsbR2c GA6g== X-Gm-Message-State: APjAAAXB9IXzmBo+jBTZOPWm9kwzohhDrxnSfCbhYwI6r1i/xR/Hlm5N BSLA+Ro1y7zcv/iYpkoN0YyQc0hk X-Google-Smtp-Source: APXvYqwA0Si8wLmRdHFkukG9fA90zpbvMJfbA/iiZueka53583tN4yxCnKdOoBJdwJsU/9etXRsogQ== X-Received: by 2002:adf:dd8c:: with SMTP id x12mr12748060wrl.262.1553422205972; Sun, 24 Mar 2019 03:10:05 -0700 (PDT) Received: from ?IPv6:2003:ea:8bc4:dc00:5ca8:2950:7dd3:94a3? (p200300EA8BC4DC005CA829507DD394A3.dip0.t-ipconnect.de. [2003:ea:8bc4:dc00:5ca8:2950:7dd3:94a3]) by smtp.googlemail.com with ESMTPSA id v20sm21609530wmj.2.2019.03.24.03.10.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Mar 2019 03:10:05 -0700 (PDT) Subject: [PATCH v2 net-next 2/3] net: phy: aquantia: report PHY details like firmware version From: Heiner Kallweit To: Andrew Lunn , Florian Fainelli , David Miller Cc: "netdev@vger.kernel.org" References: <6c552924-6ec3-d339-232e-97aa8ac4b443@gmail.com> Message-ID: <46240f6b-62bc-3538-b1e6-c758701ae0e0@gmail.com> Date: Sun, 24 Mar 2019 11:08:13 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.0 MIME-Version: 1.0 In-Reply-To: <6c552924-6ec3-d339-232e-97aa8ac4b443@gmail.com> Content-Language: en-US Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add reporting firmware details. These details are available only once the firmware has finished initializing the chip. This can take some time and we need to poll for init completion. v2: - Propagate timeout in aqr107_wait_reset_complete(). Don't bail out completely on timeout because chip may be functional even w/o firmware image. Signed-off-by: Heiner Kallweit --- drivers/net/phy/aquantia_main.c | 62 +++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c index 48d63dd1a..1a8cdb67c 100644 --- a/drivers/net/phy/aquantia_main.c +++ b/drivers/net/phy/aquantia_main.c @@ -70,6 +70,14 @@ #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) /* Vendor specific 1, MDIO_MMD_VEND1 */ +#define VEND1_GLOBAL_FW_ID 0x0020 +#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) +#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) + +#define VEND1_GLOBAL_RSVD_STAT1 0xc885 +#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) +#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) + #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 @@ -349,14 +357,64 @@ static int aqr107_set_tunable(struct phy_device *phydev, } } +/* If we configure settings whilst firmware is still initializing the chip, + * then these settings may be overwritten. Therefore make sure chip + * initialization has completed. Use presence of the firmware ID as + * indicator for initialization having completed. + * The chip also provides a "reset completed" bit, but it's cleared after + * read. Therefore function would time out if called again. + */ +static int aqr107_wait_reset_complete(struct phy_device *phydev) +{ + int val, retries = 100; + + do { + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); + if (val < 0) + return val; + msleep(20); + } while (!val && --retries); + + return val ? 0 : -ETIMEDOUT; +} + +static void aqr107_chip_info(struct phy_device *phydev) +{ + u8 fw_major, fw_minor, build_id, prov_id; + int val; + + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); + if (val < 0) + return; + + fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); + fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); + + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); + if (val < 0) + return; + + build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); + prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); + + phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", + fw_major, fw_minor, build_id, prov_id); +} + static int aqr107_config_init(struct phy_device *phydev) { + int ret; + /* Check that the PHY interface type is compatible */ if (phydev->interface != PHY_INTERFACE_MODE_SGMII && phydev->interface != PHY_INTERFACE_MODE_2500BASEX && phydev->interface != PHY_INTERFACE_MODE_10GKR) return -ENODEV; + ret = aqr107_wait_reset_complete(phydev); + if (!ret) + aqr107_chip_info(phydev); + /* ensure that a latched downshift event is cleared */ aqr107_read_downshift_event(phydev); @@ -372,6 +430,10 @@ static int aqcs109_config_init(struct phy_device *phydev) phydev->interface != PHY_INTERFACE_MODE_2500BASEX) return -ENODEV; + ret = aqr107_wait_reset_complete(phydev); + if (!ret) + aqr107_chip_info(phydev); + /* AQCS109 belongs to a chip family partially supporting 10G and 5G. * PMA speed ability bits are the same for all members of the family, * AQCS109 however supports speeds up to 2.5G only.