Patchwork [U-Boot,v2,2/2] gpio: Add GPIO driver for Marvell SoC Armada100

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Submitter Ajay Bhargav
Date July 22, 2011, 7:16 a.m.
Message ID <1311318994-20660-2-git-send-email-ajay.bhargav@einfochips.com>
Download mbox | patch
Permalink /patch/106233/
State Superseded
Headers show

Comments

Ajay Bhargav - July 22, 2011, 7:16 a.m.
This patch adds support for generic GPIO driver framework for Marvell
SoC Armada100.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
---
 arch/arm/include/asm/arch-armada100/armada100.h |    4 +
 arch/arm/include/asm/arch-armada100/gpio.h      |   95 +++++++++++++++++++++++
 2 files changed, 99 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
Ajay Bhargav - July 22, 2011, 7:27 a.m.
Hi Lei,

> Why not put this structure into driver file?
> I think this register is not easy to change, and put this into arch
> .h
> would make the work duplicated,
> as each arch need to redefine the same structure again.
> 
Other architectures may/may not have the same structure. One can redefine
structure based on this header file.

Thanks & Regards,
Ajay Bhargav
Lei Wen - July 22, 2011, 7:30 a.m.
Hi Ajay,

On Fri, Jul 22, 2011 at 3:16 PM, Ajay Bhargav
<ajay.bhargav@einfochips.com> wrote:
> This patch adds support for generic GPIO driver framework for Marvell
> SoC Armada100.
>
> Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
> ---
>  arch/arm/include/asm/arch-armada100/armada100.h |    4 +
>  arch/arm/include/asm/arch-armada100/gpio.h      |   95 +++++++++++++++++++++++
>  2 files changed, 99 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
>
> diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
> index d5d125a..aad3ed1 100644
> --- a/arch/arm/include/asm/arch-armada100/armada100.h
> +++ b/arch/arm/include/asm/arch-armada100/armada100.h
> @@ -59,6 +59,10 @@
>  #define ARMD1_MPMU_BASE                0xD4050000
>  #define ARMD1_APMU_BASE                0xD4282800
>  #define ARMD1_CPU_BASE         0xD4282C00
> +#define ARMD1_GPIO0_BASE       0xD4019000
> +#define ARMD1_GPIO1_BASE       0xD4019004
> +#define ARMD1_GPIO2_BASE       0xD4019008
> +#define ARMD1_GPIO3_BASE       0xD4019100
>
>  /*
>  * Main Power Management (MPMU) Registers
> diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h
> new file mode 100644
> index 0000000..0593b13
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-armada100/gpio.h
> @@ -0,0 +1,95 @@
> +/*
> + * (C) Copyright 2011
> + * eInfochips Ltd. <www.einfochips.com>
> + * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
> + *
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _ASM_ARCH_GPIO_H
> +#define _ASM_ARCH_GPIO_H
> +
> +#include <asm/types.h>
> +#include <asm/arch/armada100.h>
> +
> +#define GPIO_TO_REG(gp)                (gp >> 5)
> +#define GPIO_TO_BIT(gp)                (1 << (gp & 0x1F))
> +#define GPIO_VAL(gp, val)      ((val >> (gp & 0x1F)) & 0x01)
> +
> +#define GPIO_SET               1
> +#define GPIO_CLR               0
> +
> +/*
> + * GPIO register map
> + * Refer Datasheet Appendix A.36
> + */
> +struct gpio_reg {

Why not put this structure into driver file?
I think this register is not easy to change, and put this into arch .h
would make the work duplicated,
as each arch need to redefine the same structure again.


> +static inline struct gpio_reg *get_gpio_base(int bank)

After put the structure into the driver file, you could simply return
void* instead of gpio_reg*.

Best regards,
Lei
Lei Wen - July 22, 2011, 7:52 a.m.
On Fri, Jul 22, 2011 at 3:27 PM, Ajay Bhargav
<ajay.bhargav@einfochips.com> wrote:
> Hi Lei,
>
>> Why not put this structure into driver file?
>> I think this register is not easy to change, and put this into arch
>> .h
>> would make the work duplicated,
>> as each arch need to redefine the same structure again.
>>
> Other architectures may/may not have the same structure. One can redefine
> structure based on this header file.

I think if have no such same structure, the gpio driver may need to be rewrite,
since the meaning of the register may also change.

Best regards,
Lei

Patch

diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
index d5d125a..aad3ed1 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -59,6 +59,10 @@ 
 #define ARMD1_MPMU_BASE		0xD4050000
 #define ARMD1_APMU_BASE		0xD4282800
 #define ARMD1_CPU_BASE		0xD4282C00
+#define ARMD1_GPIO0_BASE	0xD4019000
+#define ARMD1_GPIO1_BASE	0xD4019004
+#define ARMD1_GPIO2_BASE	0xD4019008
+#define ARMD1_GPIO3_BASE	0xD4019100
 
 /*
  * Main Power Management (MPMU) Registers
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 0000000..0593b13
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,95 @@ 
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include <asm/types.h>
+#include <asm/arch/armada100.h>
+
+#define GPIO_TO_REG(gp)		(gp >> 5)
+#define GPIO_TO_BIT(gp)		(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val)	((val >> (gp & 0x1F)) & 0x01)
+
+#define GPIO_SET		1
+#define GPIO_CLR		0
+
+/*
+ * GPIO register map
+ * Refer Datasheet Appendix A.36
+ */
+struct gpio_reg {
+	u32 gplr;	/* Pin Level Register - 0x0000 */
+	u32 pad0[2];
+	u32 gpdr;	/* Pin Direction Register - 0x000C */
+	u32 pad1[2];
+	u32 gpsr;	/* Pin Output Set Register - 0x0018 */
+	u32 pad2[2];
+	u32 gpcr;	/* Pin Output Clear Register - 0x0024 */
+	u32 pad3[2];
+	u32 grer;	/* Rising-Edge Detect Enable Register - 0x0030 */
+	u32 pad4[2];
+	u32 gfer;	/* Falling-Edge Detect Enable Register - 0x003C */
+	u32 pad5[2];
+	u32 gedr;	/* Edge Detect Status Register - 0x0048 */
+	u32 pad6[2];
+	u32 gsdr;	/* Bitwise Set of GPIO Direction Register - 0x0054 */
+	u32 pad7[2];
+	u32 gcdr;	/* Bitwise Clear of GPIO Direction Register - 0x0060 */
+	u32 pad8[2];
+	u32 gsrer;	/* Bitwise Set of Rising-Edge Detect Enable
+			   Register - 0x006C */
+	u32 pad9[2];
+	u32 gcrer;	/* Bitwise Clear of Rising-Edge Detect Enable
+			   Register - 0x0078 */
+	u32 pad10[2];
+	u32 gsfer;	/* Bitwise Set of Falling-Edge Detect Enable
+			   Register - 0x0084 */
+	u32 pad11[2];
+	u32 gcfer;	/* Bitwise Clear of Falling-Edge Detect Enable
+			   Register - 0x0090 */
+	u32 pad12[2];
+	u32 apmask;	/* Bitwise Mask of Edge Detect Register - 0x009C */
+};
+
+
+static inline struct gpio_reg *get_gpio_base(int bank)
+{
+	switch (bank) {
+	case 0:
+		return (struct gpio_reg *)ARMD1_GPIO0_BASE;
+	case 1:
+		return (struct gpio_reg *)ARMD1_GPIO1_BASE;
+	case 2:
+		return (struct gpio_reg *)ARMD1_GPIO2_BASE;
+	case 3:
+		return (struct gpio_reg *)ARMD1_GPIO3_BASE;
+	}
+	return 0;
+}
+
+#endif /* _ASM_ARCH_GPIO_H */