From patchwork Thu Jul 21 15:16:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsuneo Saito X-Patchwork-Id: 106089 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8EF73B6F77 for ; Fri, 22 Jul 2011 02:06:34 +1000 (EST) Received: from localhost ([::1]:58930 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qjv39-0002M6-B1 for incoming@patchwork.ozlabs.org; Thu, 21 Jul 2011 11:20:31 -0400 Received: from eggs.gnu.org ([140.186.70.92]:51930) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qjv2b-00019R-QN for qemu-devel@nongnu.org; Thu, 21 Jul 2011 11:19:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qjv02-00033Y-4K for qemu-devel@nongnu.org; Thu, 21 Jul 2011 11:17:19 -0400 Received: from mail-pv0-f173.google.com ([74.125.83.173]:36877) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qjv01-00032p-SE for qemu-devel@nongnu.org; Thu, 21 Jul 2011 11:17:18 -0400 Received: by mail-pv0-f173.google.com with SMTP id 3so1492044pvg.4 for ; Thu, 21 Jul 2011 08:17:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=zHLioIzSn1cGMZbECuuZ7pHreIQTEFN+J9wNRqF5AOE=; b=v+0u1G8QaixT2PifOOqomVaG4zg4+6sw2Evz4JnMnQ/JyjwcT9Itco5y4vhuMcrAB6 dYhSAUJhyWXIzrd8kXOsj6aLjhIFxChQloF6Y9C9PmweF6SwxYkjptXVPEu1s89v1jtE 8l4PCSgsAL/aRuD/I3AxIDdr+7qHyi1kLx6qk= Received: by 10.68.34.164 with SMTP id a4mr485016pbj.33.1311261437384; Thu, 21 Jul 2011 08:17:17 -0700 (PDT) Received: from localhost.localdomain (tetkyo149119.tkyo.te.ftth2.ppp.infoweb.ne.jp [202.219.195.119]) by mx.google.com with ESMTPS id g4sm948229pbj.73.2011.07.21.08.17.16 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 21 Jul 2011 08:17:17 -0700 (PDT) From: Tsuneo Saito To: qemu-devel@nongnu.org Date: Fri, 22 Jul 2011 00:16:33 +0900 Message-Id: <1311261393-47400-8-git-send-email-tsnsaito@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1311261393-47400-1-git-send-email-tsnsaito@gmail.com> References: <1311261393-47400-1-git-send-email-tsnsaito@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.83.173 Cc: Tsuneo Saito Subject: [Qemu-devel] [PATCH 7/7] SPARC64: implement addtional MMU faults related to nonfaulting load X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch implements MMU faults caused by TTE.NFO and TTE.E: - access other than nonfaulting load to a page marked NFO should raise data_access_exception - nonfaulting load to a page marked with E bit should raise data_access_exception To distinguish nonfaulting loads, this patch extends (abuses?) the rw argument of get_physical_address_data(). rw is set to 4 on nonfaulting loads. Signed-off-by: Tsuneo Saito --- target-sparc/cpu.h | 4 ++++ target-sparc/helper.c | 29 ++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index f4eeff5..a51863c 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -290,15 +290,19 @@ enum { #endif #define TTE_VALID_BIT (1ULL << 63) +#define TTE_NFO_BIT (1ULL << 60) #define TTE_USED_BIT (1ULL << 41) #define TTE_LOCKED_BIT (1ULL << 6) +#define TTE_SIDEEFFECT_BIT (1ULL << 3) #define TTE_PRIV_BIT (1ULL << 2) #define TTE_W_OK_BIT (1ULL << 1) #define TTE_GLOBAL_BIT (1ULL << 0) #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) +#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) +#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) diff --git a/target-sparc/helper.c b/target-sparc/helper.c index b6e62a7..acc07f5 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -445,27 +445,50 @@ static int get_physical_address_data(CPUState *env, if (rw == 1) { sfsr |= SFSR_WRITE_BIT; + } else if (rw == 4) { + sfsr |= SFSR_NF_BIT; } for (i = 0; i < 64; i++) { // ctx match, vaddr match, valid? if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) { + int do_fault = 0; // access ok? + /* multiple bits in SFSR.FT may be set on TT_DFAULT */ if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) { + do_fault = 1; sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */ - env->exception_index = TT_DFAULT; DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64 " mmu_idx=%d tl=%d\n", address, context, mmu_idx, env->tl); + } + if (rw == 4) { + if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) { + do_fault = 1; + sfsr |= SFSR_FT_NF_E_BIT; + } + } else { + if (TTE_IS_NFO(env->dtlb[i].tte)) { + do_fault = 1; + sfsr |= SFSR_FT_NFO_BIT; + } + } + + if (do_fault) { + /* faults above are reported with TT_DFAULT. */ + env->exception_index = TT_DFAULT; } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { + do_fault = 1; env->exception_index = TT_DPROT; DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64 " mmu_idx=%d tl=%d\n", address, context, mmu_idx, env->tl); - } else { + } + + if (!do_fault) { *prot = PAGE_READ; if (TTE_IS_W_OK(env->dtlb[i].tte)) { *prot |= PAGE_WRITE; @@ -752,7 +775,7 @@ target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr, { target_phys_addr_t phys_addr; - if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) { + if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) { return -1; } return phys_addr;