From patchwork Thu Jul 21 15:06:03 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Williams X-Patchwork-Id: 106080 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EE3DFB6F71 for ; Fri, 22 Jul 2011 01:06:32 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1647B2810C; Thu, 21 Jul 2011 17:06:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bA2mAvseTh9R; Thu, 21 Jul 2011 17:06:30 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0418828116; Thu, 21 Jul 2011 17:06:28 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 36B3428116 for ; Thu, 21 Jul 2011 17:06:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZUKoNUFeLQRa for ; Thu, 21 Jul 2011 17:06:24 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qw0-f44.google.com (mail-qw0-f44.google.com [209.85.216.44]) by theia.denx.de (Postfix) with ESMTPS id A63602810C for ; Thu, 21 Jul 2011 17:06:21 +0200 (CEST) Received: by qwc23 with SMTP id 23so683698qwc.3 for ; Thu, 21 Jul 2011 08:06:19 -0700 (PDT) Received: by 10.229.98.20 with SMTP id o20mr295383qcn.216.1311260779217; Thu, 21 Jul 2011 08:06:19 -0700 (PDT) Received: from localhost.localdomain (158-147-143-21.harris.com [158.147.143.21]) by mx.google.com with ESMTPS id b6sm895132qcb.35.2011.07.21.08.06.17 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 21 Jul 2011 08:06:17 -0700 (PDT) From: Mike Williams To: u-boot@lists.denx.de Date: Thu, 21 Jul 2011 11:06:03 -0400 Message-Id: <1311260763-15422-1-git-send-email-mike@mikebwilliams.com> X-Mailer: git-send-email 1.7.3.4 Subject: [U-Boot] [PATCH] ppc460: read get_sys_info from CPR registers instead of STRP registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This code has been changed to read the CPU speed information from the CPR registers rather than the bootstrap registers. This is useful when changing the clock speed to something other than the default on boot. Signed-off-by: Mike Williams --- arch/powerpc/cpu/ppc4xx/speed.c | 33 +++++++++++++------------------ arch/powerpc/include/asm/ppc460ex_gt.h | 15 +++++++++++++- 2 files changed, 28 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 09d6671..2643fc0 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -328,38 +328,33 @@ void get_sys_info(sys_info_t *sysInfo) */ void get_sys_info (sys_info_t * sysInfo) { - unsigned long strp0; - unsigned long strp1; + unsigned long pllc, plld, plbed, opbd, perd; unsigned long temp; unsigned long m; unsigned long plbedv0; /* Extract configured divisors */ - mfsdr(SDR0_SDSTP0, strp0); - mfsdr(SDR0_SDSTP1, strp1); - - temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4); - sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); - - temp = (strp0 & PLLSYS0_FWD_DIV_B_MASK); - sysInfo->pllFwdDivB = get_cpr0_fwdv(temp); - temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 8; - sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); + mfcpr(CPR0_PLLD, plld); + sysInfo->pllFwdDivA = get_cpr0_fwdv((plld & PLLD_FWDVA_MASK) >> 16); + sysInfo->pllFwdDivB = get_cpr0_fwdv((plld & PLLD_FWDVB_MASK) >> 8); + sysInfo->pllFbkDiv = get_cpr0_fbdv((plld & PLLD_FBDV_MASK) >> 24); - temp = (strp1 & PLLSYS0_OPB_DIV_MASK) >> 26; + mfcpr(CPR0_OPBD0, opbd); + temp = ((opbd & OPBDV_MASK) >> 24); sysInfo->pllOpbDiv = temp ? temp : 4; - /* AMCC_TODO: verify the SDR0_SDSTP1.PERDV0 value sysInfo->pllExtBusDiv */ - temp = (strp1 & PLLSYS0_PERCLK_DIV_MASK) >> 24; + mfcpr(CPR0_PERD, perd); + temp = ((perd & PERDV_MASK) >> 24); sysInfo->pllExtBusDiv = temp ? temp : 4; - temp = (strp1 & PLLSYS0_PLBEDV0_DIV_MASK) >> 29; - plbedv0 = temp ? temp: 8; + mfcpr(CPR0_PLBED, plbed); + temp = ((plbed & PLBEDDV_MASK) >> 24); + plbedv0 = temp ? temp : 8; /* Calculate 'M' based on feedback source */ - temp = (strp0 & PLLSYS0_SEL_MASK) >> 27; - if (temp == 0) { + mfcpr(CPR0_PLLC, pllc); + if (((pllc & PLLC_FBSEL_MASK) >> 24) == 0) { /* PLL internal feedback */ m = sysInfo->pllFbkDiv; } else { diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h index 732fcac..cff22ad 100644 --- a/arch/powerpc/include/asm/ppc460ex_gt.h +++ b/arch/powerpc/include/asm/ppc460ex_gt.h @@ -211,11 +211,24 @@ #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ -#define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_PLBED 0x00000080 /* PLL PLB Early Clock Divider */ + +#define CPR0_ICFG_RLI_MASK 0x80000000 /* CPR Reset Load Inhibit */ #define CPR0_PLLC_RST 0x80000000 #define CPR0_PLLC_ENG 0x40000000 +#define PLLC_FBSEL_MASK 0x03000000 /* PLLC Feedback Selection */ + +#define PLLD_FBDV_MASK 0xff000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ + +#define PLBEDDV_MASK 0x07000000 /* PLB Early Divisor */ +#define OPBDV_MASK 0x03000000 /* OPB Clock Divisor */ +#define PERDV_MASK 0x03000000 /* Peripheral Clock Divisor */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + #define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) #define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)