Patchwork [U-Boot,1/3] powerpc/85xx: Rename P2040 id & SERDES to P2041

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Submitter Kumar Gala
Date July 21, 2011, 5:20 a.m.
Message ID <1311225621-9674-2-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/105917/
State Accepted
Delegated to: Kumar Gala
Headers show

Comments

Kumar Gala - July 21, 2011, 5:20 a.m.
P2041 is the superset part that covers both P2040 & P2041.  The only
Kumar Gala - July 27, 2011, 2:57 a.m.
On Jul 21, 2011, at 12:20 AM, Kumar Gala wrote:

> P2041 is the superset part that covers both P2040 & P2041.  The only
> difference between the two devices is that P2041 supports 10g/XAUI and
> has an L2 cache.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/Makefile       |    6 +-
> arch/powerpc/cpu/mpc85xx/p2040_ids.c    |  109 -------------------------------
> arch/powerpc/cpu/mpc85xx/p2040_serdes.c |   90 -------------------------
> arch/powerpc/cpu/mpc85xx/p2041_ids.c    |  109 +++++++++++++++++++++++++++++++
> arch/powerpc/cpu/mpc85xx/p2041_serdes.c |   90 +++++++++++++++++++++++++
> 5 files changed, 202 insertions(+), 202 deletions(-)
> delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_ids.c
> delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_serdes.c
> create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_ids.c
> create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_serdes.c

applied to 85xx

- k

Patch

difference between the two devices is that P2041 supports 10g/XAUI and
has an L2 cache.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/Makefile       |    6 +-
 arch/powerpc/cpu/mpc85xx/p2040_ids.c    |  109 -------------------------------
 arch/powerpc/cpu/mpc85xx/p2040_serdes.c |   90 -------------------------
 arch/powerpc/cpu/mpc85xx/p2041_ids.c    |  109 +++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/p2041_serdes.c |   90 +++++++++++++++++++++++++
 5 files changed, 202 insertions(+), 202 deletions(-)
 delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_ids.c
 delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_serdes.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_ids.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 222ea7e..d6ec611 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -78,8 +78,8 @@  COBJS-$(CONFIG_PCI)	+= pci.o
 COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
-COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o
-COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
+COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
@@ -113,7 +113,7 @@  COBJS-$(CONFIG_P1024)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1025)	+= p1021_serdes.o
 COBJS-$(CONFIG_P2010)	+= p2020_serdes.o
 COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
-COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/p2040_ids.c b/arch/powerpc/cpu/mpc85xx/p2040_ids.c
deleted file mode 100644
index 112ea56..0000000
--- a/arch/powerpc/cpu/mpc85xx/p2040_ids.c
+++ /dev/null
@@ -1,109 +0,0 @@ 
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
-	/* dqrr liodn, frame data liodn, liodn off, sdest */
-	SET_QP_INFO( 1,  2,  1, 0),
-	SET_QP_INFO( 3,  4,  2, 1),
-	SET_QP_INFO( 5,  6,  3, 2),
-	SET_QP_INFO( 7,  8,  4, 3),
-	SET_QP_INFO( 9, 10,  5, 4),
-	SET_QP_INFO( 0,  0,  0, 5),
-	SET_QP_INFO( 0,  0,  0, 6),
-	SET_QP_INFO( 0,  0,  0, 7),
-	SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
-	SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
-};
-#endif
-
-struct liodn_id_table liodn_tbl[] = {
-#ifdef CONFIG_SYS_DPAA_QBMAN
-	SET_QMAN_LIODN(31),
-	SET_BMAN_LIODN(32),
-#endif
-
-	SET_SDHC_LIODN(1, 64),
-
-	SET_PME_LIODN(117),
-
-	SET_USB_LIODN(1, "fsl-usb2-mph", 125),
-	SET_USB_LIODN(2, "fsl-usb2-dr", 126),
-
-	SET_SATA_LIODN(1, 127),
-	SET_SATA_LIODN(2, 128),
-
-	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
-	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
-	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
-
-	SET_DMA_LIODN(1, 197),
-	SET_DMA_LIODN(2, 198),
-
-	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
-	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
-	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
-	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
-};
-int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-struct liodn_id_table fman1_liodn_tbl[] = {
-	SET_FMAN_RX_1G_LIODN(1, 0, 10),
-	SET_FMAN_RX_1G_LIODN(1, 1, 11),
-	SET_FMAN_RX_1G_LIODN(1, 2, 12),
-	SET_FMAN_RX_1G_LIODN(1, 3, 13),
-	SET_FMAN_RX_1G_LIODN(1, 4, 14),
-#if (CONFIG_SYS_NUM_FM1_10GEC == 1)
-	SET_FMAN_RX_10G_LIODN(1, 0, 15),
-#endif
-};
-int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-#endif
-
-struct liodn_id_table sec_liodn_tbl[] = {
-	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
-	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
-	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
-	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
-	SET_SEC_RTIC_LIODN_ENTRY(a, 154),
-	SET_SEC_RTIC_LIODN_ENTRY(b, 155),
-	SET_SEC_RTIC_LIODN_ENTRY(c, 156),
-	SET_SEC_RTIC_LIODN_ENTRY(d, 157),
-	SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
-	SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
-};
-int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
-
-struct liodn_id_table liodn_bases[] = {
-	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 100),
-#ifdef CONFIG_SYS_DPAA_FMAN
-	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
-#endif
-#ifdef CONFIG_SYS_DPAA_PME
-	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(136, 172),
-#endif
-};
diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c
deleted file mode 100644
index 83bc82f..0000000
--- a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c
+++ /dev/null
@@ -1,90 +0,0 @@ 
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_serdes.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "fsl_corenet_serdes.h"
-
-static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
-	[0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
-		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
-	[0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
-		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
-	[0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
-		SATA2, NONE, NONE, NONE, NONE, },
-	[0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE,
-		NONE, NONE, NONE, NONE, NONE, NONE, },
-	[0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
-		PCIE3, NONE, NONE, NONE, NONE, },
-	[0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
-		SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
-		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
-	[0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
-		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
-		NONE, NONE, NONE, },
-	[0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
-		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
-		NONE, NONE, NONE, },
-	[0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
-		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE,
-		NONE, NONE, NONE, NONE, NONE, },
-	[0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
-		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
-	[0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
-		SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
-		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
-	[0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
-		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
-		SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
-};
-
-enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
-{
-	if (!serdes_lane_enabled(lane))
-		return NONE;
-
-	return serdes_cfg_tbl[cfg][lane];
-}
-
-int is_serdes_prtcl_valid(u32 prtcl)
-{
-	int i;
-
-	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
-		return 0;
-
-	for (i = 0; i < SRDS_MAX_LANES; i++) {
-		if (serdes_cfg_tbl[prtcl][i] != NONE)
-			return 1;
-	}
-
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
new file mode 100644
index 0000000..112ea56
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
@@ -0,0 +1,109 @@ 
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO( 1,  2,  1, 0),
+	SET_QP_INFO( 3,  4,  2, 1),
+	SET_QP_INFO( 5,  6,  3, 2),
+	SET_QP_INFO( 7,  8,  4, 3),
+	SET_QP_INFO( 9, 10,  5, 4),
+	SET_QP_INFO( 0,  0,  0, 5),
+	SET_QP_INFO( 0,  0,  0, 6),
+	SET_QP_INFO( 0,  0,  0, 7),
+	SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
+	SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(31),
+	SET_BMAN_LIODN(32),
+#endif
+
+	SET_SDHC_LIODN(1, 64),
+
+	SET_PME_LIODN(117),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 125),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 126),
+
+	SET_SATA_LIODN(1, 127),
+	SET_SATA_LIODN(2, 128),
+
+	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
+	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
+	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
+
+	SET_DMA_LIODN(1, 197),
+	SET_DMA_LIODN(2, 198),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 10),
+	SET_FMAN_RX_1G_LIODN(1, 1, 11),
+	SET_FMAN_RX_1G_LIODN(1, 2, 12),
+	SET_FMAN_RX_1G_LIODN(1, 3, 13),
+	SET_FMAN_RX_1G_LIODN(1, 4, 14),
+#if (CONFIG_SYS_NUM_FM1_10GEC == 1)
+	SET_FMAN_RX_10G_LIODN(1, 0, 15),
+#endif
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 154),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 155),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 156),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 157),
+	SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
+	SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+struct liodn_id_table liodn_bases[] = {
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 100),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(136, 172),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
new file mode 100644
index 0000000..83bc82f
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
@@ -0,0 +1,90 @@ 
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+	[0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+	[0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+	[0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
+		SATA2, NONE, NONE, NONE, NONE, },
+	[0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE,
+		NONE, NONE, NONE, NONE, NONE, NONE, },
+	[0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
+		PCIE3, NONE, NONE, NONE, NONE, },
+	[0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+		SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+	[0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
+		NONE, NONE, NONE, },
+	[0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
+		NONE, NONE, NONE, },
+	[0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE,
+		NONE, NONE, NONE, NONE, NONE, },
+	[0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
+		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
+	[0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+		SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
+		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
+	[0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
+		SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+	if (!serdes_lane_enabled(lane))
+		return NONE;
+
+	return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl)
+{
+	int i;
+
+	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_cfg_tbl[prtcl][i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}