From patchwork Wed Jul 20 20:32:55 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105912 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2B494B6F76 for ; Thu, 21 Jul 2011 15:06:29 +1000 (EST) Received: from localhost ([::1]:49346 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qje08-0001Sb-Le for incoming@patchwork.ozlabs.org; Wed, 20 Jul 2011 17:08:16 -0400 Received: from eggs.gnu.org ([140.186.70.92]:41940) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QjdSD-0004o5-IH for qemu-devel@nongnu.org; Wed, 20 Jul 2011 16:33:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QjdS8-0005JI-Fv for qemu-devel@nongnu.org; Wed, 20 Jul 2011 16:33:13 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:38408) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QjdS7-0005IM-M5 for qemu-devel@nongnu.org; Wed, 20 Jul 2011 16:33:08 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1QjdRv-0002an-Hs; Wed, 20 Jul 2011 21:32:55 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 20 Jul 2011 21:32:55 +0100 Message-Id: <1311193975-9938-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1311193975-9938-1-git-send-email-peter.maydell@linaro.org> References: <1311193975-9938-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Jamie Iles , Paul Brook , Aurelien Jarno , patches@linaro.org Subject: [Qemu-devel] [PATCH 2/2] target-arm: Mark 1136r1 as a v6K core X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such, thus enabling the TLS registers, NOP hints, CLREX, half and byte wide exclusive load/stores, etc. The VA-to-PA translation registers are not present on 1136r1, so introduce a new feature flag for them, which is enabled on 1176, 11MPCore and all v7 cores. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 1 + target-arm/helper.c | 22 ++++++++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1e74eb8..961a489 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -368,6 +368,7 @@ enum arm_features { ARM_FEATURE_V4T, ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, + ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target-arm/helper.c b/target-arm/helper.c index cff7c6f..755a60d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -76,13 +76,24 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; - case ARM_CPUID_ARM1136_R2: case ARM_CPUID_ARM1136: + /* This is the 1136 r1, which is a v6K core */ + set_feature(env, ARM_FEATURE_V6K); + /* Fall through */ + case ARM_CPUID_ARM1136_R2: + /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an + * older core than plain "arm1136". In particular this does not + * have the v6K features. + */ set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); + /* These ID register values are correct for 1136 but may be wrong + * for 1136_r2 (in particular r0p2 does not actually implement most + * of the ID registers). + */ env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; @@ -98,6 +109,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); + set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; @@ -113,6 +125,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); + set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; @@ -243,6 +256,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) cpu_abort(env, "Bad CPU ID: %x\n", id); break; } + + /* Some features automatically imply others: */ + if (arm_feature(env, ARM_FEATURE_V7)) { + set_feature(env, ARM_FEATURE_VAPA); + } } void cpu_reset(CPUARMState *env) @@ -1520,7 +1538,7 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) goto bad_reg; } /* No cache, so nothing to do except VA->PA translations. */ - if (arm_feature(env, ARM_FEATURE_V6K)) { + if (arm_feature(env, ARM_FEATURE_VAPA)) { switch (crm) { case 4: if (arm_feature(env, ARM_FEATURE_V7)) {