[PULL,17/19] target/riscv: Remove unused struct

Message ID	20190319124803.13826-18-palmer@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> Date: Tue, 19 Mar 2019 05:48:01 -0700 Message-Id: <20190319124803.13826-18-palmer@sifive.com> In-Reply-To: <20190319124803.13826-1-palmer@sifive.com> References: <20190319124803.13826-1-palmer@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 17/19] target/riscv: Remove unused struct Precedence: list Cc: Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/19] RISC-V: Add 32-bit gdb xml files. \| expand [PULL,01/19] RISC-V: Add 32-bit gdb xml files. [PULL,02/19] RISC-V: Add 64-bit gdb xml files. [PULL,03/19] RISC-V: Fixes to CSR_* register macros. [PULL,04/19] RISC-V: Add debug support for accessing CSRs. [PULL,05/19] RISC-V: Add hooks to use the gdb xml files. [PULL,06/19] riscv: pmp: Log pmp access errors as guest errors [PULL,07/19] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC [PULL,08/19] RISC-V: Allow interrupt controllers to claim interrupts [PULL,09/19] RISC-V: Remove unnecessary disassembler constraints [PULL,10/19] elf: Add RISC-V PSABI ELF header defines [PULL,11/19] RISC-V: linux-user support for RVE ABI [PULL,12/19] RISC-V: Change local interrupts from edge to level [PULL,13/19] RISC-V: Add support for vectored interrupts [PULL,14/19] RISC-V: Convert trap debugging to trace events [PULL,15/19] RISC-V: Update load reservation comment in do_interrupt [PULL,16/19] riscv: sifive_u: Allow up to 4 CPUs to be created [PULL,17/19] target/riscv: Remove unused struct [PULL,18/19] riscv: sifive_uart: Generate TX interrupt [PULL,19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree

Message ID

20190319124803.13826-18-palmer@sifive.com

State

New

Headers

Date: Tue, 19 Mar 2019 05:48:01 -0700
Message-Id: <20190319124803.13826-18-palmer@sifive.com>
In-Reply-To: <20190319124803.13826-1-palmer@sifive.com>
References: <20190319124803.13826-1-palmer@sifive.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Subject: [Qemu-devel] [PULL 17/19] target/riscv: Remove unused struct
Precedence: list
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

[PULL,01/19] RISC-V: Add 32-bit gdb xml files. | expand

Commit Message

Palmer Dabbelt March 19, 2019, 12:48 p.m. UTC

From: Alistair Francis <Alistair.Francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/cpu.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index feea169e1223..d61bce6d5581 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -80,12 +80,6 @@  const char * const riscv_intr_names[] = {
     "reserved"
 };
 
-typedef struct RISCVCPUInfo {
-    const int bit_widths;
-    const char *name;
-    void (*initfn)(Object *obj);
-} RISCVCPUInfo;
-
 static void set_misa(CPURISCVState *env, target_ulong misa)
 {
     env->misa_mask = env->misa = misa;

[PULL,17/19] target/riscv: Remove unused struct

Commit Message

Patch