Patchwork [U-Boot,v3,upstream] powerpc/85xx: Adding configuration for DCSRCR to enable 32M access

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Submitter Stephen George
Date July 20, 2011, 2:47 p.m.
Message ID <1311173246-27063-1-git-send-email-stephen.george@freescale.com>
Download mbox | patch
Permalink /patch/105698/
State Accepted
Commit f110fe940c7bca04cf0104952555fd931b075fac
Delegated to: Kumar Gala
Headers show

Comments

Stephen George - July 20, 2011, 2:47 p.m.
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Most DCSR registers are within 4M but the Nexus trace buffer
is located at offset 16M within the DCSR.

Configuring the LAW to be 32M to allow access to the Nexus
trace buffer. No TLB modification is required since accessing
the Nexus trace buffer from within u-boot is not required.

Signed-off-by: Stephen George <stephen.george@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |   11 +++++++++++
 arch/powerpc/include/asm/immap_85xx.h |    7 ++++++-
 board/freescale/corenet_ds/law.c      |    3 ++-
 3 files changed, 19 insertions(+), 2 deletions(-)
Kumar Gala - July 20, 2011, 3:06 p.m.
On Jul 20, 2011, at 9:47 AM, Stephen George wrote:

> Configuring DCSRCR to define the DCSR space to be 1G instead
> of the default 4M. DCSRCR only allows selection of either 4M
> or 1G.
> Most DCSR registers are within 4M but the Nexus trace buffer
> is located at offset 16M within the DCSR.
> 
> Configuring the LAW to be 32M to allow access to the Nexus
> trace buffer. No TLB modification is required since accessing
> the Nexus trace buffer from within u-boot is not required.
> 
> Signed-off-by: Stephen George <stephen.george@freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/cpu_init.c   |   11 +++++++++++
> arch/powerpc/include/asm/immap_85xx.h |    7 ++++++-
> board/freescale/corenet_ds/law.c      |    3 ++-
> 3 files changed, 19 insertions(+), 2 deletions(-)

in the future:

1. when posting upstream (reset internal counter [v3])
2. don't CC internal list
3. dont need [upstream] in the subject

- k
Kumar Gala - July 27, 2011, 2:58 a.m.
On Jul 20, 2011, at 9:47 AM, Stephen George wrote:

> Configuring DCSRCR to define the DCSR space to be 1G instead
> of the default 4M. DCSRCR only allows selection of either 4M
> or 1G.
> Most DCSR registers are within 4M but the Nexus trace buffer
> is located at offset 16M within the DCSR.
> 
> Configuring the LAW to be 32M to allow access to the Nexus
> trace buffer. No TLB modification is required since accessing
> the Nexus trace buffer from within u-boot is not required.
> 
> Signed-off-by: Stephen George <stephen.george@freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/cpu_init.c   |   11 +++++++++++
> arch/powerpc/include/asm/immap_85xx.h |    7 ++++++-
> board/freescale/corenet_ds/law.c      |    3 ++-
> 3 files changed, 19 insertions(+), 2 deletions(-)

applied to 85xx

- k

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6becd5b..36d5cf5 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -223,6 +223,10 @@  static void corenet_tb_init(void)
 void cpu_init_f (void)
 {
 	extern void m8560_cpm_reset (void);
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+
 #ifdef CONFIG_MPC8548
 	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	uint svr = get_svr();
@@ -270,6 +274,13 @@  void cpu_init_f (void)
 
 	/* Invalidate the CPC before DDR gets enabled */
 	invalidate_cpc();
+
+ #ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* set DCSRCR so that DCSR space is 1G */
+	setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
+	in_be32(&gur->dcsrcr);
+#endif
+
 }
 
 /* Implement a dummy function for those platforms w/o SERDES */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index abba9f5..398d9d2 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1772,7 +1772,8 @@  typedef struct ccsr_gur {
 	u32	cgencrl;	/* Core general control */
 	u8	res31[184];
 	u32	sriopstecr;	/* SRIO prescaler timer enable control */
-	u8	res32[1788];
+	u32	dcsrcr;		/* DCSR Control register */
+	u8	res32[1784];
 	u32	pmuxcr;		/* Pin multiplexing control */
 	u8	res33[60];
 	u32	iovselsr;	/* I/O voltage selection status */
@@ -1785,6 +1786,10 @@  typedef struct ccsr_gur {
 	u8	res37[380];
 } ccsr_gur_t;
 
+#define FSL_CORENET_DCSR_SZ_MASK	0x00000003
+#define FSL_CORENET_DCSR_SZ_4M		0x0
+#define FSL_CORENET_DCSR_SZ_1G		0x3
+
 /*
  * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
  * everything after has RMan thus msg unit LIODN is used for maintenance
diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c
index dd6f6f7..58f23c5 100644
--- a/board/freescale/corenet_ds/law.c
+++ b/board/freescale/corenet_ds/law.c
@@ -37,7 +37,8 @@  struct law_entry law_table[] = {
 #endif
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),