From patchwork Thu Mar 14 22:45:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1056720 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-100657-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="Evz/PSud"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44L3hc55m8z9sBF for ; Fri, 15 Mar 2019 09:45:52 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id; q=dns; s= default; b=nujHqqMoLdF6ZBgITmwDAfTGPKW7sjOc2hl+AfofRJmlPxvTT5lQU 1GHgY6iB+1+dBfPuccxXTQbnodZLRHI/gG5aF2DpShZsg/djf1R41SqOef/tpl/N 2iWcY3lUUxPf3L2YJskQsAcdC/vnOnXh+6sa7OCueepmdhsqiFnN9M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id; s=default; bh=JzGg0hv3KDJKKBz/A1Dg08/g5L0=; b=Evz/PSud0NiQuhOb6jQ525A74qnC JR/zNPmzGBGvtWgw03FeRAXR4UOH2nU/DRwYC55eUJYDHL5VcA54du3hbEiYIpxx Kkl3yxvTWGnX8b1ZjkW0tAYWRE6i9qY0x4UCDjDOotPVPZpWebYtYRsEdwvcnJ8B xL2pwq1qDqlfnQM= Received: (qmail 95321 invoked by alias); 14 Mar 2019 22:45:46 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 95306 invoked by uid 89); 14 Mar 2019 22:45:46 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KHOP_DYNAMIC, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy=ud, HX-Languages-Length:4493 X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@linux.ibm.com Subject: [PATCH] [powerpc] Use __builtin_{mffs,mtfsf} Date: Thu, 14 Mar 2019 18:45:38 -0400 x-cbid: 19031422-0052-0000-0000-0000039B56DA X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010759; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000281; SDB=6.01174423; UDB=6.00614115; IPR=6.00955088; MB=3.00025981; MTD=3.00000008; XFM=3.00000015; UTC=2019-03-14 22:45:40 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031422-0053-0000-0000-000060282800 Message-Id: <1552603538-23024-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" Replace inline asm uses of the "mffs" and "mtfsf" instructions with the analogous GCC builtins. __builtin_mffs and __builtin_mtfsf are both available in GCC 5 and above. Given the minimum GCC level for GLibC is now GCC 6.2, it is safe to use these builtins without restriction. 2019-03-14 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_register): Replace inline asm with builtin. * sysdeps/powerpc/fpu_control.h (_FPU_GETCW): Likewise. (_FPU_SETCW): Likewise. * sysdeps/powerpc/powerpc64/le/fpu/sfp-machine.h (FP_INIT_ROUNDMODE): Likewise. * sysdeps/powerpc/fpu/tst-setcontext-fpscr.c (_GET_DI_FPSCR): Likewise. (_GET_SI_FPSCR): Likewise. (_SET_SI_FPSCR): Likewise. --- sysdeps/powerpc/fpu/fenv_libc.h | 5 ++--- sysdeps/powerpc/fpu/tst-setcontext-fpscr.c | 10 +++------- sysdeps/powerpc/fpu_control.h | 8 ++------ sysdeps/powerpc/powerpc64/le/fpu/sfp-machine.h | 3 +-- 4 files changed, 8 insertions(+), 18 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 67a9c9a..8a0bace 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -32,8 +32,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; /* Equivalent to fegetenv, but returns a fenv_t instead of taking a pointer. */ -#define fegetenv_register() \ - ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; }) +#define fegetenv_register() __builtin_mffs() /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */ #define fesetenv_register(env) \ @@ -45,7 +44,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; "mtfsf 0xff,%0,1,0; " \ ".machine pop" : : "f" (d)); \ else \ - asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \ + __builtin_mtfsf (0xff, d); \ } while(0) /* This very handy macro: diff --git a/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c b/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c index 958afff..7dfd5a9 100644 --- a/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c +++ b/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c @@ -97,9 +97,7 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__))); /* Macros for accessing the hardware control word on Power6[x]. */ #define _GET_DI_FPSCR(__fpscr) \ ({union { double d; di_fpscr_t fpscr; } u; \ - register double fr; \ - __asm__ ("mffs %0" : "=f" (fr)); \ - u.d = fr; \ + u.d = __builtin_mffs (); \ (__fpscr) = u.fpscr; \ u.fpscr; \ }) @@ -121,9 +119,7 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__))); # define _GET_SI_FPSCR(__fpscr) \ ({union { double d; di_fpscr_t fpscr; } u; \ - register double fr; \ - __asm__ ("mffs %0" : "=f" (fr)); \ - u.d = fr; \ + u.d = __builtin_mffs (); \ (__fpscr) = (si_fpscr_t) u.fpscr; \ (si_fpscr_t) u.fpscr; \ }) @@ -137,7 +133,7 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__))); u.fpscr = 0xfff80000ULL << 32; \ u.fpscr |= __fpscr & 0xffffffffULL; \ fr = u.d; \ - __asm__ ("mtfsf 255,%0" : : "f" (fr)); \ + __builtin_mtfsf (255, fr); \ fr = 0.0; \ } diff --git a/sysdeps/powerpc/fpu_control.h b/sysdeps/powerpc/fpu_control.h index e0c5cf6..a48d3cc 100644 --- a/sysdeps/powerpc/fpu_control.h +++ b/sysdeps/powerpc/fpu_control.h @@ -96,20 +96,16 @@ typedef unsigned int fpu_control_t; /* Macros for accessing the hardware control word. */ # define _FPU_GETCW(cw) \ ({union { double __d; unsigned long long __ll; } __u; \ - register double __fr; \ - __asm__ ("mffs %0" : "=f" (__fr)); \ - __u.__d = __fr; \ + __u.__d = __builtin_mffs (); \ (cw) = (fpu_control_t) __u.__ll; \ (fpu_control_t) __u.__ll; \ }) # define _FPU_SETCW(cw) \ { union { double __d; unsigned long long __ll; } __u; \ - register double __fr; \ __u.__ll = 0xfff80000LL << 32; /* This is a QNaN. */ \ __u.__ll |= (cw) & 0xffffffffLL; \ - __fr = __u.__d; \ - __asm__ ("mtfsf 255,%0" : : "f" (__fr)); \ + __builtin_mtfsf (255, __u.__d); \ } /* Default control word set at startup. */ diff --git a/sysdeps/powerpc/powerpc64/le/fpu/sfp-machine.h b/sysdeps/powerpc/powerpc64/le/fpu/sfp-machine.h index ac74097..b4b27f9 100644 --- a/sysdeps/powerpc/powerpc64/le/fpu/sfp-machine.h +++ b/sysdeps/powerpc/powerpc64/le/fpu/sfp-machine.h @@ -107,8 +107,7 @@ void __sfp_handle_exceptions (int); #define FP_INIT_ROUNDMODE \ do { \ - __asm__ __volatile__ ("mffs %0" \ - : "=f" (_fpscr.d)); \ + _fpscr.d = __builtin_mffs (); \ } while (0) # define FP_ROUNDMODE (_fpscr.i & FP_RND_MASK)