From patchwork Wed Jul 20 08:19:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 105596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id EA05FB6F77 for ; Wed, 20 Jul 2011 18:19:40 +1000 (EST) Received: (qmail 1335 invoked by alias); 20 Jul 2011 08:19:36 -0000 Received: (qmail 1327 invoked by uid 22791); 20 Jul 2011 08:19:35 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-pv0-f175.google.com (HELO mail-pv0-f175.google.com) (74.125.83.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 20 Jul 2011 08:19:18 +0000 Received: by pvf24 with SMTP id 24so4995518pvf.20 for ; Wed, 20 Jul 2011 01:19:17 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.80.3 with SMTP id d3mr937385wfb.363.1311149957197; Wed, 20 Jul 2011 01:19:17 -0700 (PDT) Received: by 10.142.89.19 with HTTP; Wed, 20 Jul 2011 01:19:17 -0700 (PDT) In-Reply-To: References: <20110719044537.GA3605@intel.com> <4E25BAF5.1000900@redhat.com> <4E25BE14.8010306@redhat.com> Date: Wed, 20 Jul 2011 10:19:17 +0200 Message-ID: Subject: Re: PATCH [7/n] X32: Handle address output and calls patterns From: Uros Bizjak To: "H.J. Lu" Cc: Richard Henderson , gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Wed, Jul 20, 2011 at 9:53 AM, Uros Bizjak wrote: >>>>> since Pmode is used in non-PIC tablejump, we have to put 64bit value for >>>>> labels with 0 upper 32bits in tablejump for x32. >>>> >>>> The mode is completely controled by CASE_VECTOR_MODE. >>>> >>> >>> Here is the updated patch.  OK for trunk? >>> >> >> A small change.  It always use 64bit register for indirect branch. > > -         ix86_print_operand (file, x, 0); > +         /* Always use 64bit register for indirect branch.  */ > +         ix86_print_operand (file, x, > +                             REG_P (x) && TARGET_64BIT ? 'q' : 0); >          return; > > /* Always use 64bit register for indirect branch.  */ > if (REG_P (x) && TARGET_64BIT) >  print_reg (x, 'q', file); > else >  ix86_print_operand (file, x, 0); > >  (define_insn "*indirect_jump" > -  [(set (pc) (match_operand:P 0 "nonimmediate_operand" "rm"))] > +  [(set (pc) (match_operand:P 0 "x32_indirect_branch_operand" "rm"))] > > Just name it "indirect_branch_operand". > >  (define_insn_and_split "*call_vzeroupper" > -  [(call (mem:QI (match_operand:P 0 "call_insn_operand" "zm")) > +  [(call (mem:QI (match_operand:P 0 "x32_call_insn_operand" "zm")) > > Don't introduce new predicate, change call_insn_operand instead to > conditionally disable memory_operand on x32. You will need to change > "zm" register constraint to "z" on x32, otherwise you will get > ICEs. Use new constraint here, something like (untested): Uros. Index: constraints.md =================================================================== --- constraints.md (revision 176494) +++ constraints.md (working copy) @@ -127,6 +127,11 @@ "@internal Constant call address operand." (match_operand 0 "constant_call_address_operand")) +(define_constraint "w" + "@internal Call memory operand." + (and (match_test "!TARGET_X32") + (match_operand 0 "memory_operand")) + ;; Integer constant constraints. (define_constraint "I" "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."