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[U-Boot,PATCHv2,2/6] ARM: pl310: Add macro's for handling tag and data latency mask

Message ID 20190312144110.18841-3-dinguyen@kernel.org
State Superseded
Delegated to: Tom Rini
Headers show
Series dm: cache: add dm cache driver | expand

Commit Message

Dinh Nguyen March 12, 2019, 2:41 p.m. UTC 
Add the PL310 macros for latency control setup, read and write bits.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 arch/arm/include/asm/pl310.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Simon Glass March 22, 2019, 7:53 a.m. UTC | #1 
On Tue, 12 Mar 2019 at 22:41, Dinh Nguyen <dinguyen@kernel.org> wrote:
>
> Add the PL310 macros for latency control setup, read and write bits.
>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
>  arch/arm/include/asm/pl310.h | 3 +++
>  1 file changed, 3 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>
diff mbox series

Patch

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@ 
 #define L310_SHARED_ATT_OVERRIDE_ENABLE		(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK	(1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK	(1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n)		((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)			((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)			((n) << 8)
 
 #define L2X0_CACHE_ID_PART_MASK     (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310     (3 << 6)