Patchwork [PATCHv2] target-arm: support for ARM1176JZF-s cores

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Submitter Jamie Iles
Date July 19, 2011, 12:32 p.m.
Message ID <1311078767-25177-1-git-send-email-jamie@jamieiles.com>
Download mbox | patch
Permalink /patch/105471/
State New
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Comments

Jamie Iles - July 19, 2011, 12:32 p.m.
Add support for v6K ARM1176JZF-S.  This core includes the VA<->PA
translation capability and security extensions.

v2: Model the version with the VFP

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Paul Brook <paul@codesourcery.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
 target-arm/cpu.h    |    1 +
 target-arm/helper.c |   23 +++++++++++++++++++++++
 2 files changed, 24 insertions(+), 0 deletions(-)
Peter Maydell - July 20, 2011, 2:35 p.m.
On 19 July 2011 13:32, Jamie Iles <jamie@jamieiles.com> wrote:
> Add support for v6K ARM1176JZF-S.  This core includes the VA<->PA
> translation capability and security extensions.

> +static uint32_t arm1176_cp15_c0_c1[8] =
> +{ 0x111, 0x11, 0x33, 0x01130003, 0x01130003, 0x10030302, 0x01222100, 0 };

This seems to be the wrong value for the AUXFR0 (0,c0,c1,3 : fourth item
in this list). The 1176JZF-S TRM says its value is 0x0, not 0x01130003
(which I think you've miscopied from the 0,c0,c1,4 MMFR0 entry).

Sorry I didn't get round to checking these numbers earlier; the
patch is otherwise fine.

-- PMM
Peter Maydell - July 20, 2011, 3:59 p.m.
On 20 July 2011 16:36, Jamie Iles <jamie@jamieiles.com> wrote:
> On Wed, Jul 20, 2011 at 03:35:19PM +0100, Peter Maydell wrote:
>> On 19 July 2011 13:32, Jamie Iles <jamie@jamieiles.com> wrote:
>> > Add support for v6K ARM1176JZF-S.  This core includes the VA<->PA
>> > translation capability and security extensions.
>>
>> > +static uint32_t arm1176_cp15_c0_c1[8] =
>> > +{ 0x111, 0x11, 0x33, 0x01130003, 0x01130003, 0x10030302, 0x01222100, 0 };
>>
>> This seems to be the wrong value for the AUXFR0 (0,c0,c1,3 : fourth item
>> in this list). The 1176JZF-S TRM says its value is 0x0, not 0x01130003
>> (which I think you've miscopied from the 0,c0,c1,4 MMFR0 entry).
>
> Ahh, yes.  Thanks for that, a good spot.

Thanks for the quick patch refresh. This version is
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

> 8<------

Incidentally, this is a bit of an unfortunate format for patches, as it
doesn't apply with the usual "git am filename". Even if you add "-c" git
still puts these headers:

> From af92ff0cd28077ff187f2ac1d952f71297b7d026 Mon Sep 17 00:00:00 2001
> From: Jamie Iles <jamie@jamieiles.com>
> Date: Thu, 23 Jun 2011 11:37:19 +0100
> Subject: [PATCHv3] target-arm: support for ARM1176JZF-s cores

into the commit log.

-- PMM
Jamie Iles - July 20, 2011, 4:06 p.m.
On Wed, Jul 20, 2011 at 04:59:29PM +0100, Peter Maydell wrote:
> On 20 July 2011 16:36, Jamie Iles <jamie@jamieiles.com> wrote:
> > On Wed, Jul 20, 2011 at 03:35:19PM +0100, Peter Maydell wrote:
> >> On 19 July 2011 13:32, Jamie Iles <jamie@jamieiles.com> wrote:
> >> > Add support for v6K ARM1176JZF-S.  This core includes the VA<->PA
> >> > translation capability and security extensions.
> >>
> >> > +static uint32_t arm1176_cp15_c0_c1[8] =
> >> > +{ 0x111, 0x11, 0x33, 0x01130003, 0x01130003, 0x10030302, 0x01222100, 0 };
> >>
> >> This seems to be the wrong value for the AUXFR0 (0,c0,c1,3 : fourth item
> >> in this list). The 1176JZF-S TRM says its value is 0x0, not 0x01130003
> >> (which I think you've miscopied from the 0,c0,c1,4 MMFR0 entry).
> >
> > Ahh, yes.  Thanks for that, a good spot.
> 
> Thanks for the quick patch refresh. This version is
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> 
> > 8<------
> 
> Incidentally, this is a bit of an unfortunate format for patches, as it
> doesn't apply with the usual "git am filename". Even if you add "-c" git
> still puts these headers:
> 
> > From af92ff0cd28077ff187f2ac1d952f71297b7d026 Mon Sep 17 00:00:00 2001
> > From: Jamie Iles <jamie@jamieiles.com>
> > Date: Thu, 23 Jun 2011 11:37:19 +0100
> > Subject: [PATCHv3] target-arm: support for ARM1176JZF-s cores
> 
> into the commit log.

Hmm, I misunderstood the scissors option, I guess a plain patch reply 
would have been best.

Thanks for the pointer (and Reviewed-by)!

Jamie

Patch

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 01f5b57..8708f9e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -414,6 +414,7 @@  void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 #define ARM_CPUID_PXA270_C5   0x69054117
 #define ARM_CPUID_ARM1136     0x4117b363
 #define ARM_CPUID_ARM1136_R2  0x4107b362
+#define ARM_CPUID_ARM1176     0x410fb767
 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 #define ARM_CPUID_CORTEXA8    0x410fc080
 #define ARM_CPUID_CORTEXA9    0x410fc090
diff --git a/target-arm/helper.c b/target-arm/helper.c
index eda881b..c5ba5a6 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -36,6 +36,12 @@  static uint32_t arm1136_cp15_c0_c1[8] =
 static uint32_t arm1136_cp15_c0_c2[8] =
 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
 
+static uint32_t arm1176_cp15_c0_c1[8] =
+{ 0x111, 0x11, 0x33, 0x01130003, 0x01130003, 0x10030302, 0x01222100, 0 };
+
+static uint32_t arm1176_cp15_c0_c2[8] =
+{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
+
 static uint32_t cpu_arm_find_by_name(const char *name);
 
 static inline void set_feature(CPUARMState *env, int feature)
@@ -86,6 +92,21 @@  static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         env->cp15.c0_cachetype = 0x1dd20d2;
         env->cp15.c1_sys = 0x00050078;
         break;
+    case ARM_CPUID_ARM1176:
+        set_feature(env, ARM_FEATURE_V4T);
+        set_feature(env, ARM_FEATURE_V5);
+        set_feature(env, ARM_FEATURE_V6);
+        set_feature(env, ARM_FEATURE_V6K);
+        set_feature(env, ARM_FEATURE_VFP);
+        set_feature(env, ARM_FEATURE_AUXCR);
+        env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
+        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
+        env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
+        memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
+        memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
+        env->cp15.c0_cachetype = 0x1dd20d2;
+        env->cp15.c1_sys = 0x00050078;
+        break;
     case ARM_CPUID_ARM11MPCORE:
         set_feature(env, ARM_FEATURE_V4T);
         set_feature(env, ARM_FEATURE_V5);
@@ -377,6 +398,7 @@  static const struct arm_cpu_t arm_cpu_names[] = {
     { ARM_CPUID_ARM1026, "arm1026"},
     { ARM_CPUID_ARM1136, "arm1136"},
     { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
+    { ARM_CPUID_ARM1176, "arm1176"},
     { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
     { ARM_CPUID_CORTEXM3, "cortex-m3"},
     { ARM_CPUID_CORTEXA8, "cortex-a8"},
@@ -1770,6 +1792,7 @@  uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
                 return 1;
             case ARM_CPUID_ARM1136:
             case ARM_CPUID_ARM1136_R2:
+            case ARM_CPUID_ARM1176:
                 return 7;
             case ARM_CPUID_ARM11MPCORE:
                 return 1;