| Message ID | 20190307223548.20516-8-clg@kaod.org |
|---|---|
| State | New |
| Headers | show |
| Series | ppc: add POWER9 support to the PowerNV platform | expand |
On Thu, Mar 07, 2019 at 11:35:40PM +0100, Cédric Le Goater wrote: > This is just a simple reminder that SerIRQ routing should be > addressed. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- Applied, thanks. > include/hw/ppc/pnv_lpc.h | 2 ++ > hw/ppc/pnv_lpc.c | 14 ++++++++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h > index 242b18081caa..413579792ed1 100644 > --- a/include/hw/ppc/pnv_lpc.h > +++ b/include/hw/ppc/pnv_lpc.h > @@ -55,6 +55,8 @@ typedef struct PnvLpcController { > MemoryRegion opb_master_regs; > > /* OPB Master LS registers */ > + uint32_t opb_irq_route0; > + uint32_t opb_irq_route1; > uint32_t opb_irq_stat; > uint32_t opb_irq_mask; > uint32_t opb_irq_pol; > diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c > index 6df694e0abc1..641e2046db92 100644 > --- a/hw/ppc/pnv_lpc.c > +++ b/hw/ppc/pnv_lpc.c > @@ -39,6 +39,8 @@ enum { > }; > > /* OPB Master LS registers */ > +#define OPB_MASTER_LS_ROUTE0 0x8 > +#define OPB_MASTER_LS_ROUTE1 0xC > #define OPB_MASTER_LS_IRQ_STAT 0x50 > #define OPB_MASTER_IRQ_LPC 0x00000800 > #define OPB_MASTER_LS_IRQ_MASK 0x54 > @@ -521,6 +523,12 @@ static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size) > uint64_t val = 0xfffffffffffffffful; > > switch (addr) { > + case OPB_MASTER_LS_ROUTE0: /* TODO */ > + val = lpc->opb_irq_route0; > + break; > + case OPB_MASTER_LS_ROUTE1: /* TODO */ > + val = lpc->opb_irq_route1; > + break; > case OPB_MASTER_LS_IRQ_STAT: > val = lpc->opb_irq_stat; > break; > @@ -547,6 +555,12 @@ static void opb_master_write(void *opaque, hwaddr addr, > PnvLpcController *lpc = opaque; > > switch (addr) { > + case OPB_MASTER_LS_ROUTE0: /* TODO */ > + lpc->opb_irq_route0 = val; > + break; > + case OPB_MASTER_LS_ROUTE1: /* TODO */ > + lpc->opb_irq_route1 = val; > + break; > case OPB_MASTER_LS_IRQ_STAT: > lpc->opb_irq_stat &= ~val; > pnv_lpc_eval_irqs(lpc);
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 242b18081caa..413579792ed1 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -55,6 +55,8 @@ typedef struct PnvLpcController { MemoryRegion opb_master_regs; /* OPB Master LS registers */ + uint32_t opb_irq_route0; + uint32_t opb_irq_route1; uint32_t opb_irq_stat; uint32_t opb_irq_mask; uint32_t opb_irq_pol; diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 6df694e0abc1..641e2046db92 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -39,6 +39,8 @@ enum { }; /* OPB Master LS registers */ +#define OPB_MASTER_LS_ROUTE0 0x8 +#define OPB_MASTER_LS_ROUTE1 0xC #define OPB_MASTER_LS_IRQ_STAT 0x50 #define OPB_MASTER_IRQ_LPC 0x00000800 #define OPB_MASTER_LS_IRQ_MASK 0x54 @@ -521,6 +523,12 @@ static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size) uint64_t val = 0xfffffffffffffffful; switch (addr) { + case OPB_MASTER_LS_ROUTE0: /* TODO */ + val = lpc->opb_irq_route0; + break; + case OPB_MASTER_LS_ROUTE1: /* TODO */ + val = lpc->opb_irq_route1; + break; case OPB_MASTER_LS_IRQ_STAT: val = lpc->opb_irq_stat; break; @@ -547,6 +555,12 @@ static void opb_master_write(void *opaque, hwaddr addr, PnvLpcController *lpc = opaque; switch (addr) { + case OPB_MASTER_LS_ROUTE0: /* TODO */ + lpc->opb_irq_route0 = val; + break; + case OPB_MASTER_LS_ROUTE1: /* TODO */ + lpc->opb_irq_route1 = val; + break; case OPB_MASTER_LS_IRQ_STAT: lpc->opb_irq_stat &= ~val; pnv_lpc_eval_irqs(lpc);
This is just a simple reminder that SerIRQ routing should be addressed. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/ppc/pnv_lpc.h | 2 ++ hw/ppc/pnv_lpc.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+)