diff mbox series

[11/27] ppc/pnv: fix logging primitives using Ox

Message ID 20190306085032.15744-12-clg@kaod.org
State New
Headers show
Series ppc: add POWER9 support to the PowerNV platform | expand

Commit Message

Cédric Le Goater March 6, 2019, 8:50 a.m. UTC 
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/pnv_lpc.c | 10 +++++-----
 hw/ppc/pnv_psi.c |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

Comments

David Gibson March 7, 2019, 3:30 a.m. UTC | #1 
On Wed, Mar 06, 2019 at 09:50:16AM +0100, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>

Wow, that's a deeply weird starting point.  Applied.

> ---
>  hw/ppc/pnv_lpc.c | 10 +++++-----
>  hw/ppc/pnv_psi.c |  4 ++--
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> index 172a915cfc55..9b18ce55e391 100644
> --- a/hw/ppc/pnv_lpc.c
> +++ b/hw/ppc/pnv_lpc.c
> @@ -294,7 +294,7 @@ static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
>          val =  lpc->lpc_hc_error_addr;
>          break;
>      default:
> -        qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
> +        qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
>                        HWADDR_PRIx "\n", addr);
>      }
>      return val;
> @@ -332,7 +332,7 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
>      case LPC_HC_ERROR_ADDRESS:
>          break;
>      default:
> -        qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
> +        qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
>                        HWADDR_PRIx "\n", addr);
>      }
>  }
> @@ -370,7 +370,7 @@ static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
>          val = lpc->opb_irq_input;
>          break;
>      default:
> -        qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
> +        qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%"
>                        HWADDR_PRIx "\n", addr);
>      }
>  
> @@ -399,8 +399,8 @@ static void opb_master_write(void *opaque, hwaddr addr,
>          /* Read only */
>          break;
>      default:
> -        qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
> -                      HWADDR_PRIx "\n", addr);
> +        qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%"
> +                      HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val);
>      }
>  }
>  
> diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
> index 44bc0cbf58cb..c872be0b9c0d 100644
> --- a/hw/ppc/pnv_psi.c
> +++ b/hw/ppc/pnv_psi.c
> @@ -323,7 +323,7 @@ static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
>          val = psi->regs[offset];
>          break;
>      default:
> -        qemu_log_mask(LOG_UNIMP, "PSI: read at Ox%" PRIx32 "\n", offset);
> +        qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
>      }
>      return val;
>  }
> @@ -382,7 +382,7 @@ static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
>          pnv_psi_set_irsn(psi, val);
>          break;
>      default:
> -        qemu_log_mask(LOG_UNIMP, "PSI: write at Ox%" PRIx32 "\n", offset);
> +        qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
>      }
>  }
>
diff mbox series

Patch

diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 172a915cfc55..9b18ce55e391 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -294,7 +294,7 @@  static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
         val =  lpc->lpc_hc_error_addr;
         break;
     default:
-        qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
+        qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
                       HWADDR_PRIx "\n", addr);
     }
     return val;
@@ -332,7 +332,7 @@  static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
     case LPC_HC_ERROR_ADDRESS:
         break;
     default:
-        qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
+        qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
                       HWADDR_PRIx "\n", addr);
     }
 }
@@ -370,7 +370,7 @@  static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
         val = lpc->opb_irq_input;
         break;
     default:
-        qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
+        qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%"
                       HWADDR_PRIx "\n", addr);
     }
 
@@ -399,8 +399,8 @@  static void opb_master_write(void *opaque, hwaddr addr,
         /* Read only */
         break;
     default:
-        qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
-                      HWADDR_PRIx "\n", addr);
+        qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%"
+                      HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val);
     }
 }
 
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 44bc0cbf58cb..c872be0b9c0d 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -323,7 +323,7 @@  static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
         val = psi->regs[offset];
         break;
     default:
-        qemu_log_mask(LOG_UNIMP, "PSI: read at Ox%" PRIx32 "\n", offset);
+        qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
     }
     return val;
 }
@@ -382,7 +382,7 @@  static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
         pnv_psi_set_irsn(psi, val);
         break;
     default:
-        qemu_log_mask(LOG_UNIMP, "PSI: write at Ox%" PRIx32 "\n", offset);
+        qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
     }
 }