From patchwork Mon Jul 18 06:15:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Lin Tang X-Patchwork-Id: 105163 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 83D7BB6F85 for ; Mon, 18 Jul 2011 16:16:03 +1000 (EST) Received: (qmail 8984 invoked by alias); 18 Jul 2011 06:15:59 -0000 Received: (qmail 8975 invoked by uid 22791); 18 Jul 2011 06:15:58 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 18 Jul 2011 06:15:36 +0000 Received: (qmail 29748 invoked from network); 18 Jul 2011 06:15:35 -0000 Received: from unknown (HELO ?192.168.1.16?) (cltang@127.0.0.2) by mail.codesourcery.com with ESMTPA; 18 Jul 2011 06:15:35 -0000 Message-ID: <4E23CF81.6070306@codesourcery.com> Date: Mon, 18 Jul 2011 14:15:29 +0800 From: Chung-Lin Tang User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 MIME-Version: 1.0 To: Richard Earnshaw CC: gcc-patches Subject: Re: [PATCH] Canonicalize compares in combine [3/3] ARM backend part References: <4DB19D15.9020509@codesourcery.com> <4DF8AFAC.4000806@arm.com> In-Reply-To: <4DF8AFAC.4000806@arm.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On 2011/6/15 09:12 PM, Richard Earnshaw wrote: > On 22/04/11 16:21, Chung-Lin Tang wrote: >> Hi Richard, this part's for you. >> >> The ARM backend changes needed are very little after the prior patches, >> basically just a case in arm_canonicalize_comparison() to detect >> (zero_extend:SI (subreg:QI (reg:SI ...) 0)), and swap it into (and:SI >> (reg:SI) #255). >> >> Had we not tried the combine modifications, this testcase probably could >> have also be solved by implementing another version of the corresponding >> *andsi3_compare0/_scratch patterns, with ZERO_EXTEND in the body, and >> "ands" in the output assembly. Maybe that's an acceptable solution too... >> >> About the (ab)use of CANONICALIZE_COMPARISON, if it really should be >> another macro/hook, then this ARM patch will need updating, but the code >> should be similar. >> >> Thanks, >> Chung-Lin >> >> >> 3-arm-parts.diff >> >> >> Index: config/arm/arm.c >> =================================================================== >> --- config/arm/arm.c (revision 172860) >> +++ config/arm/arm.c (working copy) >> @@ -3276,6 +3276,19 @@ >> return code; >> } >> >> + /* If *op0 is (zero_extend:SI (subreg:QI (reg:SI) 0)) and comparing >> + with const0_rtx, change it to (and:SI (reg:SI) (const_int 255)), >> + to facilitate possible combining with a cmp into 'ands'. */ >> + if (mode == SImode >> + && GET_CODE (*op0) == ZERO_EXTEND >> + && GET_CODE (XEXP (*op0, 0)) == SUBREG >> + && GET_MODE (XEXP (*op0, 0)) == QImode >> + && GET_MODE (SUBREG_REG (XEXP (*op0, 0))) == SImode >> + && SUBREG_BYTE (XEXP (*op0, 0)) == 0 >> + && *op1 == const0_rtx) >> + *op0 = gen_rtx_AND (SImode, SUBREG_REG (XEXP (*op0, 0)), >> + GEN_INT (255)); >> + > > This is wrong for big-endian code. You should use subreg_lowpart_p to > check the subreg expression (after you've checked that you do have a > subreg, of course). > > R. > Hi Richard, thanks for catching that. I've updated the patch, and cross-tested again under both arm/armeb-Linux. I changed the testcase to use -march=armv6t2 instead of armv6, as the latter makes the testcase FAIL when configured as --with-mode=thumb. Is this now okay? Thanks, Chung-Lin Index: config/arm/arm.c =================================================================== --- config/arm/arm.c (revision 176385) +++ config/arm/arm.c (working copy) @@ -3172,6 +3172,19 @@ return code; } + /* If *op0 is (zero_extend:SI (subreg:QI (reg:SI) 0)) and comparing + with const0_rtx, change it to (and:SI (reg:SI) (const_int 255)), + to facilitate possible combining with a cmp into 'ands'. */ + if (mode == SImode + && GET_CODE (*op0) == ZERO_EXTEND + && GET_CODE (XEXP (*op0, 0)) == SUBREG + && GET_MODE (XEXP (*op0, 0)) == QImode + && GET_MODE (SUBREG_REG (XEXP (*op0, 0))) == SImode + && subreg_lowpart_p (XEXP (*op0, 0)) + && *op1 == const0_rtx) + *op0 = gen_rtx_AND (SImode, SUBREG_REG (XEXP (*op0, 0)), + GEN_INT (255)); + /* Comparisons smaller than DImode. Only adjust comparisons against an out-of-range constant. */ if (GET_CODE (*op1) != CONST_INT Index: testsuite/gcc.target/arm/combine-movs.c =================================================================== --- testsuite/gcc.target/arm/combine-movs.c (revision 0) +++ testsuite/gcc.target/arm/combine-movs.c (revision 0) @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +void foo (unsigned long r[], unsigned int d) +{ + int i, n = d / 32; + for (i = 0; i < n; ++i) + r[i] = 0; +} + +/* { dg-final { scan-assembler "movs\tr\[0-9\]" } } */ Index: testsuite/gcc.target/arm/unsigned-extend-2.c =================================================================== --- testsuite/gcc.target/arm/unsigned-extend-2.c (revision 0) +++ testsuite/gcc.target/arm/unsigned-extend-2.c (revision 0) @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O -march=armv6t2" } */ + +unsigned short foo (unsigned short x) +{ + unsigned char i = 0; + for (i = 0; i < 8; i++) + { + x >>= 1; + x &= 0x7fff; + } + return x; +} + +/* { dg-final { scan-assembler "ands" } } */ +/* { dg-final { scan-assembler-not "uxtb" } } */ +/* { dg-final { scan-assembler-not "cmp" } } */