Message ID | 20190304181813.8075-54-cota@braap.org |
---|---|
State | New |
Headers | show
Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=braap.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=braap.org header.i=@braap.org header.b="OS69ypWh"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="aOg3wtAt"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Cpx12XTJz9ryj for <incoming@patchwork.ozlabs.org>; Tue, 5 Mar 2019 05:49:57 +1100 (AEDT) Received: from localhost ([127.0.0.1]:59022 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>) id 1h0sex-0000xW-82 for incoming@patchwork.ozlabs.org; Mon, 04 Mar 2019 13:49:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <cota@braap.org>) id 1h0sBC-0000T8-O3 for qemu-devel@nongnu.org; Mon, 04 Mar 2019 13:19:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from <cota@braap.org>) id 1h0sBB-000282-4r for qemu-devel@nongnu.org; Mon, 04 Mar 2019 13:19:10 -0500 Received: from wout2-smtp.messagingengine.com ([64.147.123.25]:57333) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from <cota@braap.org>) id 1h0sBA-0001ID-Ql for qemu-devel@nongnu.org; Mon, 04 Mar 2019 13:19:09 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id EE9E73729; Mon, 4 Mar 2019 13:18:27 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Mon, 04 Mar 2019 13:18:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=mesmtp; bh=143ov9ij4yHKF2aehV2tiQIRFhoilkER+LmxRPKE4Ro=; b=OS69ypWhUJJH kOOT8LoJZfzutdGihjdzNmbS7P/vp0v1t2V0Bf9YoJz/99SVezc1u75566mw0Kkx ogPquToszN8/FQJm3HQmIcLE94fM6L328X2x2Hh+NfPPl9RO1LupUiEqMB0v0i+5 09edon68sBGteqDAVc3KZNFAwAbxbCs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=143ov9ij4yHKF2aehV2tiQIRFhoilkER+LmxRPKE4 Ro=; b=aOg3wtAtQvlOyPOZ19oJDod5rf5hVfRDohxyjOy2Ui765lo/LV6+olnLY SmPuDDIBfzbViHkaKRr9W7Gc73LFP10XvZqlF/VxH+yzZjOvbl5MNpw+wwTwCNvC wji2bxtmzuz3t2elDkQ3sejYN/AA1fZ3eSGD2opUu/2+VhWYzQlWvkCG/IvLIef+ FjszoPeo06ULHygIkGkT+kLGnZN7qDVtAFXcZkXOCcZukyJhbQxKlifRG9MK31ZT 6MDN6LnW4aEkMLxQXB3rAkYCfcjqek2RRshirMrwK/pjuzSoxssq20fiJ5MQgerC kczGNJf7y8/yhBbSnmxAzL4TNDDIA== X-ME-Sender: <xms:82t9XKqghOQAzn5M94XKovzE-Uua1BFyRKXq5gEcR94Y3AfwsaRoWg> X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedutddrfedugdduuddtucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepfdfgmhhi lhhiohcuifdrucevohhtrgdfuceotghothgrsegsrhgrrghprdhorhhgqeenucfkphepud dvkedrheelrddvtddrvdduieenucfrrghrrghmpehmrghilhhfrhhomheptghothgrsegs rhgrrghprdhorhhgnecuvehluhhsthgvrhfuihiivgepvdeh X-ME-Proxy: <xmx:82t9XArE_N62SK8t92iTaZmLE1Q12nphPKgr0EK-DQ4fDkVd9eglaA> <xmx:82t9XP1JtaCK0O263RbEG0MGtydNT03c712casldPCpDF2ZgQofWHw> <xmx:82t9XJcB04X-GwAyEh4a_aRimZ9VEiwwIQDA8CM5fryemUY0cDdxDA> <xmx:82t9XGIM7067sCkxGyipCvTTHq4YQ6JOVi6xj4r7TCfBXBNtcmRvrg> Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 2DC2410336; Mon, 4 Mar 2019 13:18:27 -0500 (EST) From: "Emilio G. Cota" <cota@braap.org> To: qemu-devel@nongnu.org Date: Mon, 4 Mar 2019 13:17:53 -0500 Message-Id: <20190304181813.8075-54-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190304181813.8075-1-cota@braap.org> References: <20190304181813.8075-1-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 64.147.123.25 Subject: [Qemu-devel] [PATCH v7 53/73] alpha: convert to cpu_interrupt_request X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, Richard Henderson <richard.henderson@linaro.org> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
Series |
[v7,01/73] cpu: convert queued work to a QSIMPLEQ
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diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 1fd95d6c0f..cebd459251 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -42,10 +42,10 @@ static bool alpha_cpu_has_work(CPUState *cs) assume that if a CPU really wants to stay asleep, it will mask interrupts at the chipset level, which will prevent these bits from being set in the first place. */ - return cs->interrupt_request & (CPU_INTERRUPT_HARD - | CPU_INTERRUPT_TIMER - | CPU_INTERRUPT_SMP - | CPU_INTERRUPT_MCHK); + return cpu_interrupt_request(cs) & (CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); } static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)