| Message ID | 1551504025-3541-9-git-send-email-skomatineni@nvidia.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [V1,01/11] mmc: tegra: fix ddr signaling for non-ddr modes | expand |
On 2/03/19 7:20 AM, Sowjanya Komatineni wrote: > This patch adds define for CBC field mask of the register > CQHCI_SSC1. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > drivers/mmc/host/cqhci.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h > index f96d8565cc07..f1dc48c7436f 100644 > --- a/drivers/mmc/host/cqhci.h > +++ b/drivers/mmc/host/cqhci.h > @@ -88,6 +88,7 @@ > > /* send status config 1 */ > #define CQHCI_SSC1 0x40 > +#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) > > /* send status config 2 */ > #define CQHCI_SSC2 0x44 >
diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index f96d8565cc07..f1dc48c7436f 100644 --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h @@ -88,6 +88,7 @@ /* send status config 1 */ #define CQHCI_SSC1 0x40 +#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) /* send status config 2 */ #define CQHCI_SSC2 0x44
This patch adds define for CBC field mask of the register CQHCI_SSC1. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/mmc/host/cqhci.h | 1 + 1 file changed, 1 insertion(+)