Message ID | 1551504025-3541-11-git-send-email-skomatineni@nvidia.com |
---|---|
State | Changes Requested |
Headers | show
Return-Path: <linux-tegra-owner@vger.kernel.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="b6xQa4PK"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44BF4l4c32z9sMQ for <incoming@patchwork.ozlabs.org>; Sat, 2 Mar 2019 16:21:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728219AbfCBFVD (ORCPT <rfc822;incoming@patchwork.ozlabs.org>); Sat, 2 Mar 2019 00:21:03 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9852 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728205AbfCBFVC (ORCPT <rfc822; linux-tegra@vger.kernel.org>); Sat, 2 Mar 2019 00:21:02 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id <B5c7a12c70000>; Fri, 01 Mar 2019 21:21:11 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:21:01 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:21:01 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:21:01 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:21:01 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id <B5c7a12bb0001>; Fri, 01 Mar 2019 21:21:00 -0800 From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <adrian.hunter@intel.com>, <ulf.hansson@linaro.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <riteshh@codeaurora.org> CC: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <anrao@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>, Sowjanya Komatineni <skomatineni@nvidia.com> Subject: [PATCH V1 11/11] arm64: tegra: enable command queue for tegra186 sdmmc4 Date: Fri, 1 Mar 2019 21:20:25 -0800 Message-ID: <1551504025-3541-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504071; bh=CYolxqoLCYY9GqQxqJVXC12HnxUs/oA/8PqPnDjGK/E=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=b6xQa4PKmW5qlsQ+T/+sCCfAeTt0h6xJT8CUsFGdI3XjXJJlCwowrLZphs7OvESOD mEZBZmFeYO+CosM5gug99eMJIucfnr5tUWtfkP97sJ0GKzG7OTZij2qz3alKw9aUj/ 1TAunQhQtQkEU/W9jfQFDYy8KJxRdUoiFhfntPtRFmnkkpCD7I74VVt8+bar3S/8rD tmuFyACgRHGXAX+6XBaLvgFA9HNBeCQBYPuWe6WMayriicw33h9qPU/Zyu0c0W/HZ5 TB+j9aaoZtaKxkUYEiFx3GstcRF+3w7/fQz7ac2IpjAovc7wO5K24esmj36Kg7TRN8 /KyapydbpiYkg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: <linux-tegra.vger.kernel.org> X-Mailing-List: linux-tegra@vger.kernel.org |
Series |
[V1,01/11] mmc: tegra: fix ddr signaling for non-ddr modes
|
expand
|
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 472f55fe9488..6e2b6ce99df2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -321,6 +321,7 @@ nvidia,default-trim = <0x5>; nvidia,dqs-trim = <63>; mmc-hs400-1_8v; + supports-cqe; status = "disabled"; };
This patch enables command queue support for Tegra186 SDMMC4. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+)