From patchwork Sat Jul 16 16:25:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aneesh V X-Patchwork-Id: 104981 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 97ABEB6F82 for ; Sun, 17 Jul 2011 02:28:27 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1D252280B1; Sat, 16 Jul 2011 18:28:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bRmzRzp8SL5H; Sat, 16 Jul 2011 18:28:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5B046280B2; Sat, 16 Jul 2011 18:28:14 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A54CF2809B for ; Sat, 16 Jul 2011 18:28:10 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 12-DrMBjidl3 for ; Sat, 16 Jul 2011 18:28:09 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 08E1C28099 for ; Sat, 16 Jul 2011 18:28:07 +0200 (CEST) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6GGS2dR014509 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Sat, 16 Jul 2011 11:28:05 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6GGS2LD003448 for ; Sat, 16 Jul 2011 21:58:02 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Sat, 16 Jul 2011 21:58:02 +0530 Received: from localhost (a0393566pc.apr.dhcp.ti.com [172.24.137.55]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6GGRrgf009766; Sat, 16 Jul 2011 21:57:54 +0530 (IST) From: Aneesh V To: Date: Sat, 16 Jul 2011 21:55:34 +0530 Message-ID: <1310833538-14438-2-git-send-email-aneesh@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1310833538-14438-1-git-send-email-aneesh@ti.com> References: <1310833538-14438-1-git-send-email-aneesh@ti.com> MIME-Version: 1.0 Cc: santosh.shilimkar@ti.com Subject: [U-Boot] [PATCH v 1/5] omap4: add omap4460 revision detection X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Aneesh V --- arch/arm/cpu/armv7/omap4/board.c | 3 +++ arch/arm/include/asm/arch-omap4/omap4.h | 1 + arch/arm/include/asm/armv7.h | 1 + 3 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 2e5739a..17e731a 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -140,6 +140,9 @@ static void init_omap4_revision(void) case MIDR_CORTEX_A9_R1P3: *omap4_revision = OMAP4430_ES2_3; break; + case MIDR_CORTEX_A9_R2P10: + *omap4_revision = OMAP4460_ES1_0; + break; default: *omap4_revision = OMAP4430_SILICON_ID_INVALID; break; diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index 563544f..7ff46d7 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -143,6 +143,7 @@ struct s32ktimer { #define OMAP4430_ES2_1 0x44300210 #define OMAP4430_ES2_2 0x44300220 #define OMAP4430_ES2_3 0x44300230 +#define OMAP4460_ES1_0 0x44600100 /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index b5784d8..9adc563 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -29,6 +29,7 @@ #define MIDR_CORTEX_A9_R0P1 0x410FC091 #define MIDR_CORTEX_A9_R1P2 0x411FC092 #define MIDR_CORTEX_A9_R1P3 0x411FC093 +#define MIDR_CORTEX_A9_R2P10 0x412FC09A /* CCSIDR */ #define CCSIDR_LINE_SIZE_OFFSET 0