From patchwork Sat Jul 16 10:06:47 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Schocher X-Patchwork-Id: 104947 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3DCE7B6F18 for ; Sat, 16 Jul 2011 20:08:09 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E8F562814A; Sat, 16 Jul 2011 12:07:48 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QD3LCwh40MCe; Sat, 16 Jul 2011 12:07:48 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5DAF22811D; Sat, 16 Jul 2011 12:07:18 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0AAAC280F5 for ; Sat, 16 Jul 2011 12:07:05 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ci14jlQ+t41l for ; Sat, 16 Jul 2011 12:07:04 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from pollux.denx.de (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by theia.denx.de (Postfix) with ESMTP id 877E3280FD for ; Sat, 16 Jul 2011 12:06:59 +0200 (CEST) Received: by pollux.denx.de (Postfix, from userid 515) id 4FF614BFE; Sat, 16 Jul 2011 12:06:59 +0200 (CEST) From: Heiko Schocher To: u-boot@lists.denx.de Date: Sat, 16 Jul 2011 12:06:47 +0200 Message-Id: <1310810810-5322-7-git-send-email-hs@denx.de> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1310810810-5322-1-git-send-email-hs@denx.de> References: <1310810810-5322-1-git-send-email-hs@denx.de> Cc: Heiko Schocher Subject: [U-Boot] [PATCH 6/9] arm926ejs, davinci: add cpuinfo for dm365 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Heiko Schocher --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 34 ++++++++++++++++++++++--- arch/arm/include/asm/arch-davinci/pll_defs.h | 4 +++ 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 8b57205..97275ce 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -114,9 +114,11 @@ out: static unsigned pll_div(volatile void *pllbase, unsigned offset) { u32 div; + unsigned ret; - div = REG(pllbase + offset); - return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1; + div = (readl(pllbase + offset)); + ret = (div & BIT(15)) ? (1 + (div & 0x1f)) : 1; + return ret; } static inline unsigned pll_prediv(volatile void *pllbase) @@ -127,13 +129,15 @@ static inline unsigned pll_prediv(volatile void *pllbase) return 8; else return pll_div(pllbase, PLLC_PREDIV); +#elif defined(CONFIG_SOC_DM365) + return pll_div(pllbase, PLLC_PREDIV); #endif return 1; } static inline unsigned pll_postdiv(volatile void *pllbase) { -#ifdef CONFIG_SOC_DM355 +#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365) return pll_div(pllbase, PLLC_POSTDIV); #elif defined(CONFIG_SOC_DM6446) if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) @@ -152,9 +156,13 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) #endif /* the PLL might be bypassed */ - if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) { + if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) { base /= pll_prediv(pllbase); +#if defined(CONFIG_SOC_DM365) + base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff); +#else base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); +#endif base /= pll_postdiv(pllbase); } return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); @@ -165,8 +173,13 @@ int print_cpuinfo(void) /* REVISIT fetch and display CPU ID and revision information * too ... that will matter as more revisions appear. */ +#if defined(CONFIG_SOC_DM365) + printf("Cores: ARM %d MHz", + pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV)); +#else printf("Cores: ARM %d MHz", pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); +#endif #ifdef DSP_PLLDIV printf(", DSP %d MHz", @@ -175,8 +188,13 @@ int print_cpuinfo(void) printf("\nDDR: %d MHz\n", /* DDR PHY uses an x2 input clock */ +#if defined(CONFIG_SOC_DM365) + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV) + / 2); +#else pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) / 2); +#endif return 0; } @@ -186,6 +204,14 @@ unsigned int davinci_arm_clk_get() return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000; } #endif + +#if defined(CONFIG_SOC_DM365) +unsigned int davinci_clk_get(unsigned int div) +{ + return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; +} +#endif + #endif /* diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h index 5d37616..606ed0b 100644 --- a/arch/arm/include/asm/arch-davinci/pll_defs.h +++ b/arch/arm/include/asm/arch-davinci/pll_defs.h @@ -76,4 +76,8 @@ struct dv_pll_regs { #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE) +#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2)) +#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7)) + +unsigned int davinci_clk_get(unsigned int div); #endif /* _DV_PLL_DEFS_H_ */