From patchwork Fri Jul 15 22:25:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Becky Bruce X-Patchwork-Id: 104918 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9D61AB6F62 for ; Sat, 16 Jul 2011 08:26:29 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 556D52807F; Sat, 16 Jul 2011 00:26:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UotuZeUfPia7; Sat, 16 Jul 2011 00:26:28 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 94B0828080; Sat, 16 Jul 2011 00:26:25 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3B59C28081 for ; Sat, 16 Jul 2011 00:26:23 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2uZDcEh1lOL0 for ; Sat, 16 Jul 2011 00:26:22 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe003.messaging.microsoft.com [216.32.181.183]) by theia.denx.de (Postfix) with ESMTPS id 1B78228080 for ; Sat, 16 Jul 2011 00:26:20 +0200 (CEST) Received: from mail106-ch1-R.bigfish.com (216.32.181.171) by CH1EHSOBE015.bigfish.com (10.43.70.65) with Microsoft SMTP Server id 14.1.225.22; Fri, 15 Jul 2011 22:26:18 +0000 Received: from mail106-ch1 (localhost.localdomain [127.0.0.1]) by mail106-ch1-R.bigfish.com (Postfix) with ESMTP id 539F7F20064 for ; Fri, 15 Jul 2011 22:26:18 +0000 (UTC) X-SpamScore: 2 X-BigFish: VS2(zzzz1202h10c0jzz8275dhz2dh2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail106-ch1 (localhost.localdomain [127.0.0.1]) by mail106-ch1 (MessageSwitch) id 1310768748301136_12078; Fri, 15 Jul 2011 22:25:48 +0000 (UTC) Received: from CH1EHSMHS013.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.247]) by mail106-ch1.bigfish.com (Postfix) with ESMTP id 5EF291938069 for ; Fri, 15 Jul 2011 22:25:45 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS013.bigfish.com (10.43.70.13) with Microsoft SMTP Server (TLS) id 14.1.225.22; Fri, 15 Jul 2011 22:25:41 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.289.8; Fri, 15 Jul 2011 17:25:40 -0500 Received: from localhost (right.am.freescale.net [10.82.193.13]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p6FMPe4x013534 for ; Fri, 15 Jul 2011 17:25:40 -0500 (CDT) From: Becky Bruce To: Date: Fri, 15 Jul 2011 17:25:37 -0500 Message-ID: <13107687402100-git-send-email-beckyb@kernel.crashing.org> X-Mailer: git-send-email 1.5.3.rc2.29.gc4640f In-Reply-To: <13107687392389-git-send-email-beckyb@kernel.crashing.org> References: <13107687392389-git-send-email-beckyb@kernel.crashing.org> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH 1/3] powerpc/mpc85xx: Add clear_ddr_tlbs function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This is useful when we just want to wipe out the TLBs. There's currently a function that resets the ddr tlbs to a different value; it is changed to utilize this function. The new function can be used in conjunction with setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address range as needed. Signed-off-by: Becky Bruce --- arch/powerpc/cpu/mpc85xx/cpu.c | 14 +++----------- arch/powerpc/cpu/mpc85xx/tlb.c | 29 +++++++++++++++++++++++++++++ arch/powerpc/include/asm/mmu.h | 1 + 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 53f0887..ce59c25 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -374,6 +374,8 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); +void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); + static void dump_spd_ddr_reg(void) { int i, j, k, m; @@ -460,19 +462,9 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; - phys_addr_t rpn = 0; int ddr_esel; - ptr = vstart; - - while (ptr < (vstart + size)) { - ddr_esel = find_tlb_idx((void *)ptr, 1); - if (ddr_esel != -1) { - read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); - disable_tlb(ddr_esel); - } - ptr += TSIZE_TO_BYTES(tsize); - } + clear_ddr_tlbs_phys(p_addr, size>>20); /* Setup new tlb to cover the physical address */ setup_ddr_tlbs_phys(p_addr, size>>20); diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 295f175..01a3561 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -300,4 +300,33 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) return setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } + +/* Invalidate the DDR TLBs for the requested size */ +void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) +{ + u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + u64 memsize = (u64)memsize_in_meg << 20; + + ptr = vstart; + + while (ptr < (vstart + memsize)) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } +} + +void clear_ddr_tlbs(unsigned int memsize_in_meg) +{ + clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); +} + + #endif /* !CONFIG_NAND_SPL */ diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index c01c85f..ef5076b 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -489,6 +489,7 @@ extern int find_free_tlbcam(void); extern void print_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); +extern void clear_ddr_tlbs(unsigned int memsize_in_meg); extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);