From patchwork Fri Jul 15 11:24:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurence Withers X-Patchwork-Id: 104802 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D5122B6EE8 for ; Fri, 15 Jul 2011 21:25:04 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6549528156; Fri, 15 Jul 2011 13:24:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LR1PKQWsw0-w; Fri, 15 Jul 2011 13:24:52 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3205E2813E; Fri, 15 Jul 2011 13:24:43 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BA745280FA for ; Fri, 15 Jul 2011 13:24:38 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q2uPBcyXdpNd for ; Fri, 15 Jul 2011 13:24:38 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from chrysocolla.lwithers.me.uk (chrysocolla.lwithers.me.uk [80.68.94.184]) by theia.denx.de (Postfix) with ESMTPS id 9E7A428111 for ; Fri, 15 Jul 2011 13:24:32 +0200 (CEST) Received: from 4.b.0.2.4.9.e.f.f.f.5.6.f.6.e.1.0.0.0.0.5.a.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1a5:0:1e6f:65ff:fe94:20b4] helo=rhodium.platinum.guralp.com) by chrysocolla.lwithers.me.uk with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1QhgVT-0007pv-Hi; Fri, 15 Jul 2011 11:24:31 +0000 Received: from lwithers by rhodium.platinum.guralp.com with local (Exim 4.72) (envelope-from ) id 1QhgVN-0000Pm-Vl; Fri, 15 Jul 2011 11:24:25 +0000 From: Laurence Withers To: u-boot@lists.denx.de Date: Fri, 15 Jul 2011 11:24:17 +0000 Message-Id: <1310729058-1552-4-git-send-email-lwithers@guralp.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1310729058-1552-1-git-send-email-lwithers@guralp.com> References: <1310729058-1552-1-git-send-email-lwithers@guralp.com> Subject: [U-Boot] [PATCH 3/4] DA8xx: switch an enum to defines for consistency X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de There are two main sets of LPSC constants, depending on the processor family. The DA8xx constants were given in an enum whereas the non-DA8xx constants were preprocessor defines. This commit switches the DA8xx constants to defines for consistency. Signed-off-by: Laurence Withers --- arch/arm/include/asm/arch-davinci/hardware.h | 81 +++++++++++++------------- 1 files changed, 40 insertions(+), 41 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index d5d4211..551b469 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -215,47 +215,46 @@ typedef volatile unsigned int * dv_reg_p; #else /* CONFIG_SOC_DA8XX */ -enum davinci_lpsc_ids { - DAVINCI_LPSC_TPCC = 0, - DAVINCI_LPSC_TPTC0, - DAVINCI_LPSC_TPTC1, - DAVINCI_LPSC_AEMIF, - DAVINCI_LPSC_SPI0, - DAVINCI_LPSC_MMC_SD, - DAVINCI_LPSC_AINTC, - DAVINCI_LPSC_ARM_RAM_ROM, - DAVINCI_LPSC_SECCTL_KEYMGR, - DAVINCI_LPSC_UART0, - DAVINCI_LPSC_SCR0, - DAVINCI_LPSC_SCR1, - DAVINCI_LPSC_SCR2, - DAVINCI_LPSC_DMAX, - DAVINCI_LPSC_ARM, - DAVINCI_LPSC_GEM, - /* for LPSCs in PSC1, offset from 32 for differentiation */ - DAVINCI_LPSC_PSC1_BASE = 32, - DAVINCI_LPSC_USB11, - DAVINCI_LPSC_USB20, - DAVINCI_LPSC_GPIO, - DAVINCI_LPSC_UHPI, - DAVINCI_LPSC_EMAC, - DAVINCI_LPSC_DDR_EMIF, - DAVINCI_LPSC_McASP0, - DAVINCI_LPSC_McASP1, - DAVINCI_LPSC_McASP2, - DAVINCI_LPSC_SPI1, - DAVINCI_LPSC_I2C1, - DAVINCI_LPSC_UART1, - DAVINCI_LPSC_UART2, - DAVINCI_LPSC_LCDC, - DAVINCI_LPSC_ePWM, - DAVINCI_LPSC_eCAP, - DAVINCI_LPSC_eQEP, - DAVINCI_LPSC_SCR_P0, - DAVINCI_LPSC_SCR_P1, - DAVINCI_LPSC_CR_P3, - DAVINCI_LPSC_L3_CBA_RAM -}; +#define DAVINCI_LPSC_TPCC 0 +#define DAVINCI_LPSC_TPTC0 1 +#define DAVINCI_LPSC_TPTC1 2 +#define DAVINCI_LPSC_AEMIF 3 +#define DAVINCI_LPSC_SPI0 4 +#define DAVINCI_LPSC_MMC_SD 5 +#define DAVINCI_LPSC_AINTC 6 +#define DAVINCI_LPSC_ARM_RAM_ROM 7 +#define DAVINCI_LPSC_SECCTL_KEYMGR 8 +#define DAVINCI_LPSC_UART0 9 +#define DAVINCI_LPSC_SCR0 10 +#define DAVINCI_LPSC_SCR1 11 +#define DAVINCI_LPSC_SCR2 12 +#define DAVINCI_LPSC_DMAX 13 +#define DAVINCI_LPSC_ARM 14 +#define DAVINCI_LPSC_GEM 15 + +/* for LPSCs in PSC1, offset from 32 for differentiation */ +#define DAVINCI_LPSC_PSC1_BASE 32 +#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 1) +#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 2) +#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3) +#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4) +#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5) +#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6) +#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7) +#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8) +#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9) +#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10) +#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11) +#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12) +#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13) +#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 14) +#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 15) +#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 16) +#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 17) +#define DAVINCI_LPSC_SCR_P0 (DAVINCI_LPSC_PSC1_BASE + 18) +#define DAVINCI_LPSC_SCR_P1 (DAVINCI_LPSC_PSC1_BASE + 19) +#define DAVINCI_LPSC_CR_P3 (DAVINCI_LPSC_PSC1_BASE + 20) +#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 21) #endif /* CONFIG_SOC_DA8XX */