Patchwork [U-Boot,V3] ARM: MX5: Fix broken leftover TO-2 errata workaround

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Submitter David Jander
Date July 14, 2011, 1:58 p.m.
Message ID <1310651937-29002-1-git-send-email-david@protonic.nl>
Download mbox | patch
Permalink /patch/104679/
State Accepted
Delegated to: Stefano Babic
Headers show

Comments

David Jander - July 14, 2011, 1:58 p.m.
This check was broken. r3 does not contain the silicon revision anymore, so
we need to reload it. Also, this errata only applies to i.MX51.

Signed-off-by: David Jander <david@protonic.nl>
---

Changed in this version:
  - Move patch changelog below '---' line.

 arch/arm/cpu/armv7/mx5/lowlevel_init.S |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)
Stefano Babic - July 16, 2011, 4:26 p.m.
On 07/14/2011 03:58 PM, David Jander wrote:
> This check was broken. r3 does not contain the silicon revision anymore, so
> we need to reload it. Also, this errata only applies to i.MX51.
> 
> Signed-off-by: David Jander <david@protonic.nl>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Patch

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index ee4150d..6c66b42 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -39,10 +39,14 @@ 
 	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
 	orr r0, r0, #(1 << 22)		/* disable write allocate */
 
-	cmp r3, #0x10    /* r3 contains the silicon rev */
+#if defined(CONFIG_MX51)
+	ldr r1, =0x0
+	ldr r3, [r1, #ROM_SI_REV]
+	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */
 	orrls r0, r0, #(1 << 25)
+#endif
 
 	mcr 15, 1, r0, c9, c0, 2
 .endm /* init_l2cc */