From patchwork Thu Jul 14 12:54:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Jander X-Patchwork-Id: 104672 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 47CFCB6F62 for ; Thu, 14 Jul 2011 22:54:24 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BD34528077; Thu, 14 Jul 2011 14:54:22 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id evvqqyzzyKLl; Thu, 14 Jul 2011 14:54:22 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 789F42807D; Thu, 14 Jul 2011 14:54:20 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A61062807D for ; Thu, 14 Jul 2011 14:54:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lSVRrfllxA0c for ; Thu, 14 Jul 2011 14:54:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from protonic.xs4all.nl (protonic.xs4all.nl [213.84.116.84]) by theia.denx.de (Postfix) with ESMTP id 6E7F328077 for ; Thu, 14 Jul 2011 14:54:15 +0200 (CEST) Received: from archvile.prtnl (archvile.prtnl [192.168.1.153]) by protonic.xs4all.nl (Postfix) with ESMTP id 88C1D28068; Thu, 14 Jul 2011 14:51:52 +0200 (CEST) From: David Jander To: u-boot@lists.denx.de Date: Thu, 14 Jul 2011 14:54:19 +0200 Message-Id: <1310648059-9386-1-git-send-email-david@protonic.nl> X-Mailer: git-send-email 1.7.4.1 Cc: David Jander Subject: [U-Boot] [PATCH V2] ARM: MX5: Fix broken leftover TO-2 errata workaround X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This check was broken. r3 does not contain the silicon revision anymore, so we need to reload it. Also, this errata only applies to i.MX51. Changed in this version: - Added #ifdef CONFIG_MX51 around the workaround Signed-off-by: David Jander --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index ee4150d..6c66b42 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -39,10 +39,14 @@ orr r0, r0, #(1 << 23) /* disable write allocate combine */ orr r0, r0, #(1 << 22) /* disable write allocate */ - cmp r3, #0x10 /* r3 contains the silicon rev */ +#if defined(CONFIG_MX51) + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 /* disable write combine for TO 2 and lower revs */ orrls r0, r0, #(1 << 25) +#endif mcr 15, 1, r0, c9, c0, 2 .endm /* init_l2cc */