Patchwork [U-Boot,V2] ARM: MX5: Fix broken leftover TO-2 errata workaround

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Submitter David Jander
Date July 14, 2011, 12:54 p.m.
Message ID <1310648059-9386-1-git-send-email-david@protonic.nl>
Download mbox | patch
Permalink /patch/104672/
State Accepted
Commit 6e25b6ce5d26c3c238c1dd947ef33dc38be003d8
Delegated to: Stefano Babic
Headers show

Comments

David Jander - July 14, 2011, 12:54 p.m.
This check was broken. r3 does not contain the silicon revision anymore, so
we need to reload it. Also, this errata only applies to i.MX51.

Changed in this version:
 - Added #ifdef CONFIG_MX51 around the workaround

Signed-off-by: David Jander <david@protonic.nl>
---
 arch/arm/cpu/armv7/mx5/lowlevel_init.S |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)
Stefano Babic - July 14, 2011, 12:58 p.m.
On 07/14/2011 02:54 PM, David Jander wrote:
> This check was broken. r3 does not contain the silicon revision anymore, so
> we need to reload it. Also, this errata only applies to i.MX51.
> 
> Changed in this version:
>  - Added #ifdef CONFIG_MX51 around the workaround
> 
> Signed-off-by: David Jander <david@protonic.nl>
> ---
>  arch/arm/cpu/armv7/mx5/lowlevel_init.S |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> index ee4150d..6c66b42 100644

Acked-by : Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic
Albert ARIBAUD - July 14, 2011, 1:47 p.m.
Hi David,

Le 14/07/2011 14:54, David Jander a écrit :
> This check was broken. r3 does not contain the silicon revision anymore, so
> we need to reload it. Also, this errata only applies to i.MX51.
>
> Changed in this version:
>   - Added #ifdef CONFIG_MX51 around the workaround

Please keep patch history below the commit message line '---' so that 
the history does not appear in the Git tree.

> Signed-off-by: David Jander<david@protonic.nl>
> ---

Put history here.

(please post a V3 for fixing this, not an amended V2!)

Amicalement,

Patch

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index ee4150d..6c66b42 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -39,10 +39,14 @@ 
 	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
 	orr r0, r0, #(1 << 22)		/* disable write allocate */
 
-	cmp r3, #0x10    /* r3 contains the silicon rev */
+#if defined(CONFIG_MX51)
+	ldr r1, =0x0
+	ldr r3, [r1, #ROM_SI_REV]
+	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */
 	orrls r0, r0, #(1 << 25)
+#endif
 
 	mcr 15, 1, r0, c9, c0, 2
 .endm /* init_l2cc */