From patchwork Wed Jul 13 02:44:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 104656 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6645CB6F68 for ; Thu, 14 Jul 2011 20:10:17 +1000 (EST) Received: from localhost ([::1]:35485 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QhIs0-0007kl-Iv for incoming@patchwork.ozlabs.org; Thu, 14 Jul 2011 06:10:12 -0400 Received: from eggs.gnu.org ([140.186.70.92]:43474) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QhIdw-0004or-O6 for qemu-devel@nongnu.org; Thu, 14 Jul 2011 05:55:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QhIdr-00056A-6l for qemu-devel@nongnu.org; Thu, 14 Jul 2011 05:55:40 -0400 Received: from cantor2.suse.de ([195.135.220.15]:41006 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QhIdq-00055d-7U for qemu-devel@nongnu.org; Thu, 14 Jul 2011 05:55:34 -0400 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 0C0528EFD4 for ; Thu, 14 Jul 2011 11:55:32 +0200 (CEST) From: Alexander Graf To: "qemu-devel@nongnu.org Developers" Date: Wed, 13 Jul 2011 04:44:10 +0200 Message-Id: <1310525052-22530-4-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1310525052-22530-1-git-send-email-agraf@suse.de> References: <1310525052-22530-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Subject: [Qemu-devel] [PATCH 3/5] s390x: update R and C bits in storage key X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When the s390x maps a page or writes happen to a page, the R and C bits get updated. The easiest way to implement this in qemu is to simply update them whenever we map a TLB translation and act according to the permissions. Signed-off-by: Alexander Graf --- target-s390x/cpu.h | 4 ++++ target-s390x/helper.c | 12 ++++++++++++ target-s390x/op_helper.c | 1 - 3 files changed, 16 insertions(+), 1 deletions(-) diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index d48a9b7..8ec61f8 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -819,6 +819,10 @@ struct sysib_322 { #define _PAGE_RO 0x200 /* HW read-only bit */ #define _PAGE_INVALID 0x400 /* HW invalid bit */ +#define SK_C (0x1 << 1) +#define SK_R (0x1 << 2) +#define SK_F (0x1 << 3) +#define SK_ACC_MASK (0xf << 4) /* EBCDIC handling */ diff --git a/target-s390x/helper.c b/target-s390x/helper.c index 1ce7079..f38859d 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -348,6 +348,7 @@ int mmu_translate(CPUState *env, target_ulong vaddr, int rw, uint64_t asc, target_ulong *raddr, int *flags) { int r = -1; + uint8_t *sk; *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC; vaddr &= TARGET_PAGE_MASK; @@ -390,6 +391,17 @@ out: *raddr = *raddr + env->psa; } + if (*raddr <= ram_size) { + sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE]; + if (*flags & PAGE_READ) { + *sk |= SK_R; + } + + if (*flags & PAGE_WRITE) { + *sk |= SK_C; + } + } + return r; } diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c index 245fb2c..7583172 100644 --- a/target-s390x/op_helper.c +++ b/target-s390x/op_helper.c @@ -2760,7 +2760,6 @@ uint64_t HELPER(iske)(uint64_t r2) return 0; } - /* XXX maybe use qemu's internal keys? */ return env->storage_keys[addr / TARGET_PAGE_SIZE]; }