diff mbox series

x86: (Reapply) Move AESNI generation to Skylake and Goldmont

Message ID 20190221231018.378240-1-thiago.macieira@intel.com
State New
Headers show
Series x86: (Reapply) Move AESNI generation to Skylake and Goldmont | expand

Commit Message

Thiago Macieira Feb. 21, 2019, 11:10 p.m. UTC 
This is a repeat of commit r263989, which commit r264052 accidentally
reverted.

Original commit message:

The instruction set first appeared with Westmere, but not all processors
in that and the next few generations have the instructions. According to
Wikipedia[1], the first generation in which all SKUs have AES
instructions are Skylake and Goldmont. I can't find any Skylake,
Kabylake, Kabylake-R or Cannon Lake currently listed at
https://ark.intel.com that says "Intel® AES New Instructions" "No".

[1] https://en.wikipedia.org/wiki/AES_instruction_set

2018-08-30  Thiago Macieira  <thiago.macieira@intel.com>

	* config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
	(PTA_SKYLAKE): Add PTA_AES.
	(PTA_GOLDMONT): Likewise.
---
 gcc/config/i386/i386.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

H.J. Lu Feb. 21, 2019, 11:25 p.m. UTC | #1 
On Thu, Feb 21, 2019 at 3:10 PM Thiago Macieira
<thiago.macieira@intel.com> wrote:
>
> This is a repeat of commit r263989, which commit r264052 accidentally
> reverted.
>
> Original commit message:
>
> The instruction set first appeared with Westmere, but not all processors
> in that and the next few generations have the instructions. According to
> Wikipedia[1], the first generation in which all SKUs have AES
> instructions are Skylake and Goldmont. I can't find any Skylake,
> Kabylake, Kabylake-R or Cannon Lake currently listed at
> https://ark.intel.com that says "Intel® AES New Instructions" "No".
>
> [1] https://en.wikipedia.org/wiki/AES_instruction_set
>
> 2018-08-30  Thiago Macieira  <thiago.macieira@intel.com>
>
>         * config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
>         (PTA_SKYLAKE): Add PTA_AES.
>         (PTA_GOLDMONT): Likewise.

I opened:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89444

and I will check it in for Thiago tomorrow.
H.J. Lu Feb. 22, 2019, 6:01 p.m. UTC | #2 
On Thu, Feb 21, 2019 at 3:25 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Thu, Feb 21, 2019 at 3:10 PM Thiago Macieira
> <thiago.macieira@intel.com> wrote:
> >
> > This is a repeat of commit r263989, which commit r264052 accidentally
> > reverted.
> >
> > Original commit message:
> >
> > The instruction set first appeared with Westmere, but not all processors
> > in that and the next few generations have the instructions. According to
> > Wikipedia[1], the first generation in which all SKUs have AES
> > instructions are Skylake and Goldmont. I can't find any Skylake,
> > Kabylake, Kabylake-R or Cannon Lake currently listed at
> > https://ark.intel.com that says "Intel® AES New Instructions" "No".
> >
> > [1] https://en.wikipedia.org/wiki/AES_instruction_set
> >
> > 2018-08-30  Thiago Macieira  <thiago.macieira@intel.com>
> >
> >         * config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
> >         (PTA_SKYLAKE): Add PTA_AES.
> >         (PTA_GOLDMONT): Likewise.
>
> I opened:
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89444
>
> and I will check it in for Thiago tomorrow.
>

Now, r263989 has been re-applied.  I got

FAIL: g++.target/i386/mv16.C  -std=gnu++14 execution test
FAIL: g++.target/i386/mv16.C  -std=gnu++17 execution test
FAIL: g++.target/i386/mv16.C  -std=gnu++98 execution test

On Westmere.  Shouldn't this

           case PROCESSOR_NEHALEM:
              if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AES)
                {
                  arg_str = "westmere";
                  priority = P_AES;
                }
              else

be removed?
diff mbox series

Patch

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 4fd8bc40a34..2cb16d9fbf6 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2360,7 +2360,7 @@  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
   | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
 const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
   | PTA_POPCNT;
-const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL;
 const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
   | PTA_XSAVEOPT;
 const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
@@ -2369,7 +2369,7 @@  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
   | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
 const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
   | PTA_RDSEED;
-const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
+const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT
   | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
 const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
   | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
@@ -2387,7 +2387,7 @@  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
   | PTA_AVX512F | PTA_AVX512CD;
 const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
 const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
-const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
+const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE
   | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
   | PTA_FSGSBASE;
 const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID