diff mbox series

[arm] Add support for Neoverse N1

Message ID 6b7ceca3-5361-a61c-68da-9d08e191d476@foss.arm.com
State New
Headers show
Series [arm] Add support for Neoverse N1 | expand

Commit Message

Kyrill Tkachov Feb. 21, 2019, 5:43 p.m. UTC 
Hi all,

This patch adds support for the Neoverse N1 [1]. This CPU was previously 
supported through the Ares codename.
-mcpu=ares is retained as an alias of the new -mcpu=neoverse-n1.

Bootstrapped and tested on arm-none-linux-gnueabihf.

Will commit to trunk together with the aarch64 patch if that one's approved.
Thanks,
Kyrill

[1] 
https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure

2019-02-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/arm/arm-cpus.in (ares): Rename to...
     (neoverse-n1): ... This.  Add ares as alias.
     * config/arm/arm-tables.opt: Regenerate.
     * config/arm/arm-tune.md: Likewise.
     * doc/invoke.txt (ARM Options): Document neoverse-n1.
diff mbox series

Patch

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index f53bdab8ac9d4a7e2f1ccd9831e7ed13342185ba..3a55f6ac6d2b104400554a7b05cf8d7791341461 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1331,8 +1331,9 @@  begin cpu cortex-a76
  part d0b
 end cpu cortex-a76
 
-begin cpu ares
- cname ares
+begin cpu neoverse-n1
+ cname neoversen1
+ alias !ares
  tune for cortex-a57
  tune flags LDSCHED
  architecture armv8.2-a+fp16+dotprod+simd
@@ -1340,7 +1341,7 @@  begin cpu ares
  costs cortex_a57
  vendor 41
  part d0c
-end cpu ares
+end cpu neoverse-n1
 
 # ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations
 begin cpu cortex-a75.cortex-a55
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 99feaa59187ae41c5e218ec3c484d872da06b64f..bba54aea3d604be11f71cc0e2f81e3ee11e7a8e3 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -235,7 +235,7 @@  EnumValue
 Enum(processor_type) String(cortex-a76) Value( TARGET_CPU_cortexa76)
 
 EnumValue
-Enum(processor_type) String(ares) Value( TARGET_CPU_ares)
+Enum(processor_type) String(neoverse-n1) Value( TARGET_CPU_neoversen1)
 
 EnumValue
 Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55)
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 46964376e0f8ef1e170d51752af796dec02d7d96..b9dfb66ec84219d862396c37dd6a587d4a955efe 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -44,7 +44,7 @@  (define_attr "tune"
 	cortexa73,exynosm1,xgene1,
 	cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
 	cortexa73cortexa53,cortexa55,cortexa75,
-	cortexa76,ares,cortexa75cortexa55,
+	cortexa76,neoversen1,cortexa75cortexa55,
 	cortexa76cortexa55,cortexm23,cortexm33,
 	cortexr52"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9e3199f4f87647074482962dc57d1c0c47116fc7..fd367f35daf3db4f11cd40159351579d3f108b91 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17466,9 +17466,9 @@  Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
 @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
 @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
-@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526},
-@samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te},
-@samp{xgene1}.
+@samp{neoverse-n1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2},
+@samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te},
+@samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
 
 Additionally, this option can specify that GCC should tune the performance
 of the code for a big.LITTLE system.  Permissible names are: