diff mbox series

[AArch64] Add support for Neoverse N1

Message ID 505275c5-2a76-164d-fa2c-c152a67ed456@foss.arm.com
State New
Headers show
Series [AArch64] Add support for Neoverse N1 | expand

Commit Message

Kyrill Tkachov Feb. 21, 2019, 5:42 p.m. UTC 
Hi all,

This patch adds support for the Neoverse N1 CPU [1]. This was supported 
in GCC earlier through the codename Ares,
which it now replaces. -mcpu=ares is still accepted as there's been a 
binutils release supporting it,
but the internal structures are renamed to use Neoverse N1-related 
identifiers.

Bootstrapped and tested on aarch64-none-linux-gnu.

Ok for trunk?
Thanks,
Kyrill

[1] 
https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure

2019-02-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/aarch64/aarch64.c (ares_tunings): Rename to...
     (neoversen1_tunings): ... This.
     * config/aarch64/aarch64-cores.def (ares): Change tuning to the above.
     (neoverse-n1): New CPU.
     * config/aarch64/aarch64-tune.md: Regenerate.
     * doc/invoke.txt (AArch64 Options): Document neoverse-n1.

Comments

James Greenhalgh Feb. 21, 2019, 10:42 p.m. UTC | #1 
On Thu, Feb 21, 2019 at 11:42:56AM -0600, Kyrill Tkachov wrote:
> Hi all,
> 
> This patch adds support for the Neoverse N1 CPU [1]. This was supported 
> in GCC earlier through the codename Ares,
> which it now replaces. -mcpu=ares is still accepted as there's been a 
> binutils release supporting it,
> but the internal structures are renamed to use Neoverse N1-related 
> identifiers.
> 
> Bootstrapped and tested on aarch64-none-linux-gnu.
> 
> Ok for trunk?

OK.

Thanks,
James

> 
> [1] 
> https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure
> 
> 2019-02-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
> 
>      * config/aarch64/aarch64.c (ares_tunings): Rename to...
>      (neoversen1_tunings): ... This.
>      * config/aarch64/aarch64-cores.def (ares): Change tuning to the above.
>      (neoverse-n1): New CPU.
>      * config/aarch64/aarch64-tune.md: Regenerate.
>      * doc/invoke.txt (AArch64 Options): Document neoverse-n1.
>
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 7c4bd52049e5ae33241acce37414da91abaa989c..b0c7d2f23ace1e3c3a89f4e3ab10c9ad08f56b22 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -100,7 +100,8 @@  AARCH64_CORE("thunderx2t99",  thunderx2t99,  thunderx2t99, 8_1A,  AARCH64_FL_FOR
 AARCH64_CORE("cortex-a55",  cortexa55, cortexa53, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1)
 AARCH64_CORE("cortex-a75",  cortexa75, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1)
 AARCH64_CORE("cortex-a76",  cortexa76, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1)
-AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, ares, 0x41, 0xd0c, -1)
+AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, neoversen1, 0x41, 0xd0c, -1)
+AARCH64_CORE("neoverse-n1",  neoversen1, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, neoversen1, 0x41, 0xd0c, -1)
 
 /* HiSilicon ('H') cores. */
 AARCH64_CORE("tsv110",  tsv110, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index 3273fa0ce7c87ff41d5f664cf9f47163725efa3e..5b1341525e9c2e3fe6306e7c9fef41f5d658420c 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@ 
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55"
+	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55"
 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 687611d1069c3c77fdacafad681b3b12d47e6d74..796a33e0677b933b321d8d1a193125cb894efdef 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1085,7 +1085,7 @@  static const struct tune_params thunderx2t99_tunings =
   &thunderx2t99_prefetch_tune
 };
 
-static const struct tune_params ares_tunings =
+static const struct tune_params neoversen1_tunings =
 {
   &cortexa57_extra_costs,
   &generic_addrcost_table,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 8656dfd24cc293e1f770cb3875bb6a8a99be6f54..9e3199f4f87647074482962dc57d1c0c47116fc7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15767,8 +15767,8 @@  performance of the code.  Permissible values for this option are:
 @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
 @samp{cortex-a76}, @samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor},
-@samp{qdf24xx}, @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan},
-@samp{octeontx}, @samp{octeontx81},  @samp{octeontx83},
+@samp{neoverse-n1},@samp{qdf24xx}, @samp{saphira}, @samp{phecda}, @samp{xgene1},
+@samp{vulcan}, @samp{octeontx}, @samp{octeontx81},  @samp{octeontx83},
 @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
 @samp{tsv110}, @samp{thunderxt83}, @samp{thunderx2t99},
 @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},