| Message ID | 20190221170207.17808-3-m-karicheri2@ti.com |
|---|---|
| State | Accepted |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | Add netcp networking support on K2G ICE EVM | expand |
On Thu, Feb 21, 2019 at 11:00 AM Murali Karicheri <m-karicheri2@ti.com> wrote: > > This patch updates pinmux configuration for K2G GP EVM based on > data generated by the pinmux tool at > https://dev.ti.com/pinmux/app.html#/default > > Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> > Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> > --- > board/ti/ks2_evm/mux-k2g.h | 32 +++++++++++++++++--------------- > 1 file changed, 17 insertions(+), 15 deletions(-) > > diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h > index 8c184a85ae..89c49f9e4f 100644 > --- a/board/ti/ks2_evm/mux-k2g.h > +++ b/board/ti/ks2_evm/mux-k2g.h > @@ -125,21 +125,23 @@ struct pin_cfg k2g_evm_pin_cfg[] = { > { 70, MODE(0) }, /* SOC_MMC1_SDWP */ > { 71, MODE(0) }, /* MMC1POW TP124 */ > > - /* RGMII */ > - { 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */ > - { 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */ > - { 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */ > - { 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */ > - { 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */ > - { 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */ > - { 85, MODE(1) }, /* SOC_RGMII_TXCLK */ > - { 91, MODE(1) }, /* SOC_RGMII_TXD3 */ > - { 92, MODE(1) }, /* SOC_RGMII_TXD2 */ > - { 93, MODE(1) }, /* SOC_RGMII_TXD1 */ > - { 94, MODE(1) }, /* SOC_RGMII_TXD0 */ > - { 95, MODE(1) }, /* SOC_RGMII_TXCTL */ > - { 98, MODE(0) }, /* SOC_MDIO_DATA */ > - { 99, MODE(0) }, /* SOC_MDIO_CLK */ > + /* EMAC */ > + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ > + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ > + { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */ > + { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */ > + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ > + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ > + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ > + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ > + { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */ > + { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */ > + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ Please sort by pin number. > + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ > + > + /* MDIO */ > + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ > + { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */ > > /* PWM */ > { 73, MODE(4) }, /* SOC_EHRPWM3A */ > -- > 2.17.0 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot
On Thu, Feb 21, 2019 at 12:02:02PM -0500, Murali Karicheri wrote: > This patch updates pinmux configuration for K2G GP EVM based on > data generated by the pinmux tool at > https://dev.ti.com/pinmux/app.html#/default > > Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> > Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Applied to u-boot/master, thanks!
diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h index 8c184a85ae..89c49f9e4f 100644 --- a/board/ti/ks2_evm/mux-k2g.h +++ b/board/ti/ks2_evm/mux-k2g.h @@ -125,21 +125,23 @@ struct pin_cfg k2g_evm_pin_cfg[] = { { 70, MODE(0) }, /* SOC_MMC1_SDWP */ { 71, MODE(0) }, /* MMC1POW TP124 */ - /* RGMII */ - { 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */ - { 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */ - { 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */ - { 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */ - { 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */ - { 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */ - { 85, MODE(1) }, /* SOC_RGMII_TXCLK */ - { 91, MODE(1) }, /* SOC_RGMII_TXD3 */ - { 92, MODE(1) }, /* SOC_RGMII_TXD2 */ - { 93, MODE(1) }, /* SOC_RGMII_TXD1 */ - { 94, MODE(1) }, /* SOC_RGMII_TXD0 */ - { 95, MODE(1) }, /* SOC_RGMII_TXCTL */ - { 98, MODE(0) }, /* SOC_MDIO_DATA */ - { 99, MODE(0) }, /* SOC_MDIO_CLK */ + /* EMAC */ + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */ + { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */ + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */ + { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */ + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ + + /* MDIO */ + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ + { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */ /* PWM */ { 73, MODE(4) }, /* SOC_EHRPWM3A */