From patchwork Wed Feb 20 09:32:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: dann frazier X-Patchwork-Id: 1045228 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 444C7x2BS5z9s5R; Wed, 20 Feb 2019 20:33:01 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1gwOFM-00012g-5g; Wed, 20 Feb 2019 09:32:56 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.86_2) (envelope-from ) id 1gwOFK-00011L-3S for kernel-team@lists.ubuntu.com; Wed, 20 Feb 2019 09:32:54 +0000 Received: from mail-wm1-f70.google.com ([209.85.128.70]) by youngberry.canonical.com with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.76) (envelope-from ) id 1gwOFJ-0000zd-Mn for kernel-team@lists.ubuntu.com; Wed, 20 Feb 2019 09:32:53 +0000 Received: by mail-wm1-f70.google.com with SMTP id v7so887437wme.9 for ; Wed, 20 Feb 2019 01:32:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V3AZny+JPJYFLeswXRlSA8BzSE+s5iuxgXKy4AHB8Zw=; b=I1/Pygo+ygPMuNnIZexqegXlO3bhkA3bHeczhufMGXK5FcazYBkXqXLdpl70ntCDnH EqSz8wUwGcLKoLmeOyLZl85Zbn5hktX01oigIsp54ojLpUcnanPVJmzh62Zgu8UPIQuD LAVcIvI6ZWfyXUos8M/P4qbCYrnRCyoHpr8z445lD7IQ2ongg9bE0NB8zinQf/54J9Br a++slAHHlLahMw+sStF649Pc/qfUVDwHbDre+ZYWwnL5JY37qMJgWlIyJxTZpfp0eQdS Ip35uUy4M0zkyFqZ2BBB37CMvGQjKA5OxqbxRV21KpfHok1Zhgo0npCYrt2/MnDCSfXs 6CPA== X-Gm-Message-State: AHQUAuYqliSi0bSnvCa+ryzvNRxG11n9aD+gLibAnT7sC0VBtWHJbpgI 6AHq8IX755GCOqx0Qg+i/wwh1HAZ5EX6UbRgEUVg/4GCIxG5H7j/cwf1ksAtXKxSRMvN68djTFN nfrokIjHEEdYfEoVYQav40GaCjcm0QHDgpj+2wwJm9w== X-Received: by 2002:adf:afce:: with SMTP id y14mr22868903wrd.219.1550655173045; Wed, 20 Feb 2019 01:32:53 -0800 (PST) X-Google-Smtp-Source: AHgI3IbZpZYYcdRFv1yQR2XEgz5nHFGS1bqBsEXpYz4pxlS4ySif7iSf2tTbzLf8ZiUHJp03eQu8Tw== X-Received: by 2002:adf:afce:: with SMTP id y14mr22868882wrd.219.1550655172668; Wed, 20 Feb 2019 01:32:52 -0800 (PST) Received: from xps13.canonical.com ([194.204.107.10]) by smtp.gmail.com with ESMTPSA id y20sm33570654wra.51.2019.02.20.01.32.51 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Feb 2019 01:32:51 -0800 (PST) From: dann frazier To: kernel-team@lists.ubuntu.com Subject: [PATCH 3/4][SRU Cosmic] arm64, mm, efi: Account for GICv3 LPI tables in static memblock reserve table Date: Wed, 20 Feb 2019 10:32:35 +0100 Message-Id: <20190220093236.30296-4-dann.frazier@canonical.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190220093236.30296-1-dann.frazier@canonical.com> References: <20190220093236.30296-1-dann.frazier@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ard Biesheuvel BugLink: https://bugs.launchpad.net/bugs/1816425 In the irqchip and EFI code, we have what basically amounts to a quirk to work around a peculiarity in the GICv3 architecture, which permits the system memory address of LPI tables to be programmable only once after a CPU reset. This means kexec kernels must use the same memory as the first kernel, and thus ensure that this memory has not been given out for other purposes by the time the ITS init code runs, which is not very early for secondary CPUs. On systems with many CPUs, these reservations could overflow the memblock reservation table, and this was addressed in commit: eff896288872 ("efi/arm: Defer persistent reservations until after paging_init()") However, this turns out to have made things worse, since the allocation of page tables and heap space for the resized memblock reservation table itself may overwrite the regions we are attempting to reserve, which may cause all kinds of corruption, also considering that the ITS will still be poking bits into that memory in response to incoming MSIs. So instead, let's grow the static memblock reservation table on such systems so it can accommodate these reservations at an earlier time. This will permit us to revert the above commit in a subsequent patch. [ mingo: Minor cleanups. ] Signed-off-by: Ard Biesheuvel Acked-by: Mike Rapoport Acked-by: Will Deacon Acked-by: Marc Zyngier Cc: Andrew Morton Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-arm-kernel@lists.infradead.org Cc: linux-efi@vger.kernel.org Link: http://lkml.kernel.org/r/20190215123333.21209-2-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar (backported from commit 8a5b403d71affa098009cc3dff1b2c45113021ad) [dannf: Trivial offset fixes in memblock.h, memblock.c] Signed-off-by: dann frazier --- arch/arm64/include/asm/memory.h | 11 +++++++++++ include/linux/memblock.h | 3 --- mm/memblock.c | 11 +++++++++-- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index 49d99214f43c5..156d9d2ce9f47 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -300,6 +300,17 @@ static inline void *phys_to_virt(phys_addr_t x) #define virt_addr_valid(kaddr) (_virt_addr_is_linear(kaddr) && \ _virt_addr_valid(kaddr)) +/* + * Given that the GIC architecture permits ITS implementations that can only be + * configured with a LPI table address once, GICv3 systems with many CPUs may + * end up reserving a lot of different regions after a kexec for their LPI + * tables (one per CPU), as we are forced to reuse the same memory after kexec + * (and thus reserve it persistently with EFI beforehand) + */ +#if defined(CONFIG_EFI) && defined(CONFIG_ARM_GIC_V3_ITS) +# define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + NR_CPUS + 1) +#endif + #include #endif diff --git a/include/linux/memblock.h b/include/linux/memblock.h index ca59883c83645..f3c6296285e4a 100644 --- a/include/linux/memblock.h +++ b/include/linux/memblock.h @@ -17,9 +17,6 @@ #include #include -#define INIT_MEMBLOCK_REGIONS 128 -#define INIT_PHYSMEM_REGIONS 4 - /* Definition of memblock flags. */ enum { MEMBLOCK_NONE = 0x0, /* No special request */ diff --git a/mm/memblock.c b/mm/memblock.c index 4b5d245fafc17..f4eb4639afce9 100644 --- a/mm/memblock.c +++ b/mm/memblock.c @@ -27,8 +27,15 @@ #include "internal.h" +#define INIT_MEMBLOCK_REGIONS 128 +#define INIT_PHYSMEM_REGIONS 4 + +#ifndef INIT_MEMBLOCK_RESERVED_REGIONS +# define INIT_MEMBLOCK_RESERVED_REGIONS INIT_MEMBLOCK_REGIONS +#endif + static struct memblock_region memblock_memory_init_regions[INIT_MEMBLOCK_REGIONS] __initdata_memblock; -static struct memblock_region memblock_reserved_init_regions[INIT_MEMBLOCK_REGIONS] __initdata_memblock; +static struct memblock_region memblock_reserved_init_regions[INIT_MEMBLOCK_RESERVED_REGIONS] __initdata_memblock; #ifdef CONFIG_HAVE_MEMBLOCK_PHYS_MAP static struct memblock_region memblock_physmem_init_regions[INIT_PHYSMEM_REGIONS] __initdata_memblock; #endif @@ -41,7 +48,7 @@ struct memblock memblock __initdata_memblock = { .reserved.regions = memblock_reserved_init_regions, .reserved.cnt = 1, /* empty dummy entry */ - .reserved.max = INIT_MEMBLOCK_REGIONS, + .reserved.max = INIT_MEMBLOCK_RESERVED_REGIONS, .reserved.name = "reserved", #ifdef CONFIG_HAVE_MEMBLOCK_PHYS_MAP