[01/41] i386: Allow MMX register modes in SSE registers

Message ID	20190218183657.16296-2-hjl.tools@gmail.com
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Headers	show Return-Path: <gcc-patches-return-496524-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=wIg f4bjzndAc8JCb6GLcX3UDIdIvjukaE0mquuAdM5MyhHDF0nuWYFltal7d1ocOwB5 U8n8yd0XzObxiWo2PxjrrCUDJkrJAP3He7qfv1PxdGJZNIU9z6UGnyX+7NjHj9tf mRHuDwm1x9tMLrywib0pou/lTRICkwRdmGJbBL8k= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: "H.J. Lu" <hjl.tools@gmail.com> To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak <ubizjak@gmail.com> Subject: [PATCH 01/41] i386: Allow MMX register modes in SSE registers Date: Mon, 18 Feb 2019 10:36:17 -0800 Message-Id: <20190218183657.16296-2-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	V9: Emulate MMX intrinsics with SSE \| expand [00/41] V9: Emulate MMX intrinsics with SSE [01/41] i386: Allow MMX register modes in SSE registers [02/41] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 [03/41] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX [04/41] i386: Emulate MMX plusminus/sat_plusminus with SSE [05/41] i386: Emulate MMX mulv4hi3 with SSE [06/41] i386: Emulate MMX smulv4hi3_highpart with SSE [07/41] i386: Emulate MMX mmx_pmaddwd with SSE [08/41] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE [09/41] i386: Emulate MMX <any_logic><mode>3 with SSE [10/41] i386: Emulate MMX mmx_andnot<mode>3 with SSE [11/41] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE [12/41] i386: Emulate MMX vec_dupv2si with SSE [13/41] i386: Emulate MMX pshufw with SSE [14/41] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE [15/41] i386: Emulate MMX sse_cvtpi2ps with SSE [16/41] i386: Emulate MMX mmx_pextrw with SSE [17/41] i386: Emulate MMX mmx_pinsrw with SSE [18/41] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE [19/41] i386: Emulate MMX mmx_pmovmskb with SSE [20/41] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE [21/41] i386: Emulate MMX maskmovq with SSE2 maskmovdqu [22/41] i386: Emulate MMX mmx_uavgv8qi3 with SSE [23/41] i386: Emulate MMX mmx_uavgv4hi3 with SSE [24/41] i386: Emulate MMX mmx_psadbw with SSE [25/41] i386: Emulate MMX movntq with SSE2 movntidi [26/41] i386: Emulate MMX umulv1siv1di3 with SSE2 [27/41] i386: Make _mm_empty () as NOP without MMX [28/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE [29/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE [30/41] i386: Emulate MMX ssse3_pmaddubsw with SSE [31/41] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE [32/41] i386: Emulate MMX pshufb with SSE version [33/41] i386: Emulate MMX ssse3_psign<mode>3 with SSE [34/41] i386: Emulate MMX ssse3_palignrdi with SSE [35/41] i386: Emulate MMX abs<mode>2 with SSE [36/41] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE [37/41] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE [38/41] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE [39/41] i386: Allow MMX intrinsic emulation with SSE [40/41] i386: Enable TM MMX intrinsics with SSE2 [41/41] i386: Add tests for MMX intrinsic emulations with SSE

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20190218183657.16296-2-hjl.tools@gmail.com

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Subject: [PATCH 01/41] i386: Allow MMX register modes in SSE registers
Date: Mon, 18 Feb 2019 10:36:17 -0800
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Series

V9: Emulate MMX intrinsics with SSE | expand

Commit Message

H.J. Lu Feb. 18, 2019, 6:36 p.m. UTC

In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW.  We can use SSE2 to support MMX register modes.

	PR target/89021
	* config/i386/i386-c.c (ix86_target_macros_internal): Define
	__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
	* config/i386/i386.c (ix86_set_reg_reg_cost): Add support for
	TARGET_MMX_WITH_SSE with VALID_MMX_REG_MODE.
	(ix86_vector_mode_supported_p): Likewise.
	* config/i386/i386.h (TARGET_MMX_WITH_SSE): New.
---
 gcc/config/i386/i386-c.c | 2 ++
 gcc/config/i386/i386.c   | 5 +++--
 gcc/config/i386/i386.h   | 2 ++
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 5e7e46fcebe..213e1b56c6b 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -548,6 +548,8 @@  ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     def_or_undef (parse_in, "__CLDEMOTE__");
   if (isa_flag2 & OPTION_MASK_ISA_PTWRITE)
     def_or_undef (parse_in, "__PTWRITE__");
+  if (TARGET_MMX_WITH_SSE)
+    def_or_undef (parse_in, "__MMX_WITH_SSE__");
   if (TARGET_IAMCU)
     {
       def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 0df792a41d1..eb642165264 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -40503,7 +40503,8 @@  ix86_set_reg_reg_cost (machine_mode mode)
 	  || (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
 	  || (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
 	  || (TARGET_SSE && VALID_SSE_REG_MODE (mode))
-	  || (TARGET_MMX && VALID_MMX_REG_MODE (mode)))
+	  || ((TARGET_MMX || TARGET_MMX_WITH_SSE)
+	      && VALID_MMX_REG_MODE (mode)))
 	units = GET_MODE_SIZE (mode);
     }
 
@@ -44329,7 +44330,7 @@  ix86_vector_mode_supported_p (machine_mode mode)
     return true;
   if (TARGET_AVX512F && VALID_AVX512F_REG_MODE (mode))
     return true;
-  if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
+  if ((TARGET_MMX ||TARGET_MMX_WITH_SSE) && VALID_MMX_REG_MODE (mode))
     return true;
   if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
     return true;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 4fd8bc40a34..91b233022c2 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -201,6 +201,8 @@  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_16BIT	TARGET_CODE16
 #define TARGET_16BIT_P(x)	TARGET_CODE16_P(x)
 
+#define TARGET_MMX_WITH_SSE	(TARGET_64BIT && TARGET_SSE2)
+
 #include "config/vxworks-dummy.h"
 
 #include "config/i386/i386-opts.h"

[01/41] i386: Allow MMX register modes in SSE registers

Commit Message

Patch