[26/41] i386: Emulate MMX umulv1siv1di3 with SSE2

Message ID	20190216224032.4889-27-hjl.tools@gmail.com
State	New
Headers	show Return-Path: <gcc-patches-return-496435-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=OEc tpSYqFzLZx1OhAJeqoHgZvTKtKrjmmy3smTD3aq8ZRwB+hd0jI8PjBIRp/UyIKMW zGv7UTnD1E1nWUO4ZpeDoK+6w1aLc/ACo93x2QBv+MzH2pkOXxsG97yIGYMWGKka rs+h7/st0RXC6E/DeB8xhwb26lv2hyxt6RuvpoBY= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: "H.J. Lu" <hjl.tools@gmail.com> To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak <ubizjak@gmail.com> Subject: [PATCH 26/41] i386: Emulate MMX umulv1siv1di3 with SSE2 Date: Sat, 16 Feb 2019 14:40:17 -0800 Message-Id: <20190216224032.4889-27-hjl.tools@gmail.com> In-Reply-To: <20190216224032.4889-1-hjl.tools@gmail.com> References: <20190216224032.4889-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	V8: Emulate MMX intrinsics with SSE \| expand [00/41] V8: Emulate MMX intrinsics with SSE [01/41] i386: Allow MMX register modes in SSE registers [02/41] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 [03/41] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX [04/41] i386: Emulate MMX plusminus/sat_plusminus with SSE [05/41] i386: Emulate MMX mulv4hi3 with SSE [06/41] i386: Emulate MMX smulv4hi3_highpart with SSE [07/41] i386: Emulate MMX mmx_pmaddwd with SSE [08/41] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE [09/41] i386: Emulate MMX <any_logic><mode>3 with SSE [10/41] i386: Emulate MMX mmx_andnot<mode>3 with SSE [11/41] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE [12/41] i386: Emulate MMX vec_dupv2si with SSE [13/41] i386: Emulate MMX pshufw with SSE [14/41] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE [15/41] i386: Emulate MMX sse_cvtpi2ps with SSE [16/41] i386: Emulate MMX mmx_pextrw with SSE [17/41] i386: Emulate MMX mmx_pinsrw with SSE [18/41] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE [19/41] i386: Emulate MMX mmx_pmovmskb with SSE [20/41] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE [21/41] i386: Emulate MMX maskmovq with SSE2 maskmovdqu [22/41] i386: Emulate MMX mmx_uavgv8qi3 with SSE [23/41] i386: Emulate MMX mmx_uavgv4hi3 with SSE [24/41] i386: Emulate MMX mmx_psadbw with SSE [25/41] i386: Emulate MMX movntq with SSE2 movntidi [26/41] i386: Emulate MMX umulv1siv1di3 with SSE2 [27/41] i386: Make _mm_empty () as NOP for TARGET_MMX_WITH_SSE [28/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE [29/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE [30/41] i386: Emulate MMX ssse3_pmaddubsw with SSE [31/41] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE [32/41] i386: Emulate MMX pshufb with SSE version [33/41] i386: Emulate MMX ssse3_psign<mode>3 with SSE [34/41] i386: Emulate MMX ssse3_palignrdi with SSE [35/41] i386: Emulate MMX abs<mode>2 with SSE [36/41] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE [37/41] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE [38/41] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE [39/41] i386: Allow MMX intrinsic emulation with SSE [40/41] i386: Enable TM MMX intrinsics with SSE2 [41/41] i386: Add tests for MMX intrinsic emulations with SSE

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Subject: [PATCH 26/41] i386: Emulate MMX umulv1siv1di3 with SSE2
Date: Sat, 16 Feb 2019 14:40:17 -0800
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Series

V8: Emulate MMX intrinsics with SSE | expand

Commit Message

H.J. Lu Feb. 16, 2019, 10:40 p.m. UTC

Emulate MMX umulv1siv1di3 with SSE2.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
	support.
	(*sse2_umulv1siv1di3): Add SSE2 emulation.
---
 gcc/config/i386/mmx.md | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index b06f0af984a..f27513f7f2c 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -905,30 +905,36 @@ 
         (mult:V1DI
 	  (zero_extend:V1DI
 	    (vec_select:V1SI
-	      (match_operand:V2SI 1 "nonimmediate_operand")
+	      (match_operand:V2SI 1 "register_mmxmem_operand")
 	      (parallel [(const_int 0)])))
 	  (zero_extend:V1DI
 	    (vec_select:V1SI
-	      (match_operand:V2SI 2 "nonimmediate_operand")
+	      (match_operand:V2SI 2 "register_mmxmem_operand")
 	      (parallel [(const_int 0)])))))]
-  "TARGET_SSE2"
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE2"
   "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
 
 (define_insn "*sse2_umulv1siv1di3"
-  [(set (match_operand:V1DI 0 "register_operand" "=y")
+  [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv")
         (mult:V1DI
 	  (zero_extend:V1DI
 	    (vec_select:V1SI
-	      (match_operand:V2SI 1 "nonimmediate_operand" "%0")
+	      (match_operand:V2SI 1 "register_mmxmem_operand" "%0,0,Yv")
 	      (parallel [(const_int 0)])))
 	  (zero_extend:V1DI
 	    (vec_select:V1SI
-	      (match_operand:V2SI 2 "nonimmediate_operand" "ym")
+	      (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")
 	      (parallel [(const_int 0)])))))]
-  "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
-  "pmuludq\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxmul")
-   (set_attr "mode" "DI")])
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && TARGET_SSE2
+   && ix86_binary_operator_ok (MULT, V2SImode, operands)"
+  "@
+   pmuludq\t{%2, %0|%0, %2}
+   pmuludq\t{%2, %0|%0, %2}
+   vpmuludq\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxmul,ssemul,ssemul")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_expand "mmx_<code>v4hi3"
   [(set (match_operand:V4HI 0 "register_operand")

[26/41] i386: Emulate MMX umulv1siv1di3 with SSE2

Commit Message

Patch