diff mbox series

s390.md fixes for 32-bit host

Message ID 20190216175227.GD2135@tucnak
State New
Headers show
Series s390.md fixes for 32-bit host | expand

Commit Message

Jakub Jelinek Feb. 16, 2019, 5:52 p.m. UTC 
Hi!

While looking into PR89369, I've noticed various spots in s390.md
using 1ul or 1UL which might not work properly if the host is e.g. ilp32,
even even instead of using ULL constants it is better to use
HOST_WIDE_INT_* macros for HOST_WIDE_INT contexts.

Bootstrapped/regtested on s390x-linux, ok for trunk?

2019-02-16  Jakub Jelinek  <jakub@redhat.com>

	* config/s390/s390.md (*<risbg_n>_ior_and_sr_ze,
	*<risbg_n>_<mode>_ior_and_lshiftrt, *<risbg_n>_sidi_ior_and_lshiftrt):
	Use HOST_WIDE_INT_M1U instead of ~(0ULL).
	(*<risbg_n>_and_subregdi_rotr, *<risbg_n>_and_subregdi_rotl): Use
	HOST_WIDE_INT_1U instead of 1ULL.
	(*pre_z10_extzv<mode>, *pre_z10_extv<mode>): Change mask type from int
	to unsigned HOST_WIDE_INT, use HOST_WIDE_INT_1U instead of 1ul.
	(*insv<mode><clobbercc_or_nocc>_appendbitsleft,
	z = (x << c) | (y >> d) splitters): Use HOST_WIDE_INT_1U
	instead of 1UL.
	(*insv<mode>_mem_reg, *insvdi_mem_reghigh): Use HOST_WIDE_INT_1U
	instead of 1ul.


	Jakub

Comments

Andreas Krebbel Feb. 18, 2019, 10 a.m. UTC | #1 
On 16.02.19 18:52, Jakub Jelinek wrote:
> Hi!
> 
> While looking into PR89369, I've noticed various spots in s390.md
> using 1ul or 1UL which might not work properly if the host is e.g. ilp32,
> even even instead of using ULL constants it is better to use
> HOST_WIDE_INT_* macros for HOST_WIDE_INT contexts.
> 
> Bootstrapped/regtested on s390x-linux, ok for trunk?
> 
> 2019-02-16  Jakub Jelinek  <jakub@redhat.com>
> 
> 	* config/s390/s390.md (*<risbg_n>_ior_and_sr_ze,
> 	*<risbg_n>_<mode>_ior_and_lshiftrt, *<risbg_n>_sidi_ior_and_lshiftrt):
> 	Use HOST_WIDE_INT_M1U instead of ~(0ULL).
> 	(*<risbg_n>_and_subregdi_rotr, *<risbg_n>_and_subregdi_rotl): Use
> 	HOST_WIDE_INT_1U instead of 1ULL.
> 	(*pre_z10_extzv<mode>, *pre_z10_extv<mode>): Change mask type from int
> 	to unsigned HOST_WIDE_INT, use HOST_WIDE_INT_1U instead of 1ul.
> 	(*insv<mode><clobbercc_or_nocc>_appendbitsleft,
> 	z = (x << c) | (y >> d) splitters): Use HOST_WIDE_INT_1U
> 	instead of 1UL.
> 	(*insv<mode>_mem_reg, *insvdi_mem_reghigh): Use HOST_WIDE_INT_1U
> 	instead of 1ul.

Ok. Thanks!

Andreas

> 
> --- gcc/config/s390/s390.md.jj	2019-02-15 18:54:35.037131906 +0100
> +++ gcc/config/s390/s390.md	2019-02-15 19:19:02.201945111 +0100
> @@ -3917,7 +3917,7 @@ (define_insn "*<risbg_n>_ior_and_sr_ze"
>  		 4)))]
>    "<z10_or_zEC12_cond>
>     && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
> -   && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
> +   && UINTVAL (operands[2]) == (HOST_WIDE_INT_M1U << UINTVAL (operands[4]))"
>    "<risbg_n>\t%0,%3,64-%4,63,%4+%5"
>    [(set_attr "op_type" "RIE")
>     (set_attr "z10prop" "z10_super_E1")])
> @@ -3943,7 +3943,8 @@ (define_insn "*<risbg_n>_and_subregdi_ro
>  			     (match_operand:SINT 2 "const_int_operand" "")) 0)
>  		(match_operand:DI 3 "contiguous_bitmask_operand" "")))]
>    "<z10_or_zEC12_cond>
> -   && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))"
> +   && (UINTVAL (operands[3])
> +       < (HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)))"
>    "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift
>    [(set_attr "op_type" "RIE")
>     (set_attr "z10prop" "z10_super_E1")])
> @@ -3955,7 +3956,8 @@ (define_insn "*<risbg_n>_and_subregdi_ro
>  			     (match_operand:SINT 2 "const_int_operand" "")) 0)
>  		(match_operand:DI 3 "contiguous_bitmask_operand" "")))]
>    "<z10_or_zEC12_cond>
> -   && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))"
> +   && !(UINTVAL (operands[3])
> +	& ((HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)) - 1))"
>    "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
>    [(set_attr "op_type" "RIE")
>     (set_attr "z10prop" "z10_super_E1")])
> @@ -3986,7 +3988,8 @@ (define_insn_and_split "*pre_z10_extzv<m
>  {
>    int bitsize = INTVAL (operands[2]);
>    int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
> -  int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
> +  unsigned HOST_WIDE_INT mask
> +    = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size);
>  
>    operands[1] = adjust_address (operands[1], BLKmode, 0);
>    set_mem_size (operands[1], size);
> @@ -4012,7 +4015,8 @@ (define_insn_and_split "*pre_z10_extv<mo
>  {
>    int bitsize = INTVAL (operands[2]);
>    int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
> -  int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
> +  unsigned HOST_WIDE_INT mask
> +    = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size);
>  
>    operands[1] = adjust_address (operands[1], BLKmode, 0);
>    set_mem_size (operands[1], size);
> @@ -4116,7 +4120,7 @@ (define_insn "*insv<mode><clobbercc_or_n
>  		 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
>  			     (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
>    "<z10_or_zEC12_cond>
> -   && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
> +   && UINTVAL (operands[2]) == (HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1"
>    "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4"
>    [(set_attr "op_type" "RIE")
>     (set_attr "z10prop" "z10_super_E1")])
> @@ -4131,7 +4135,8 @@ (define_insn "*<risbg_n>_<mode>_ior_and_
>  		  (match_operand:GPR 3 "register_operand" "d")
>  		  (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
>    "<z10_or_zEC12_cond> && UINTVAL (operands[2])
> -   == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
> +   == (HOST_WIDE_INT_M1U
> +       << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
>    "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4"
>    [(set_attr "op_type" "RIE")
>     (set_attr "z10prop" "z10_super_E1")])
> @@ -4147,7 +4152,7 @@ (define_insn "*<risbg_n>_sidi_ior_and_ls
>  		  (match_operand:DI 3 "register_operand" "d")
>  		  (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))]
>    "<z10_or_zEC12_cond>
> -   && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))"
> +   && UINTVAL (operands[2]) == ~(HOST_WIDE_INT_M1U >> UINTVAL (operands[4]))"
>    "<risbg_n>\t%0,%3,%4,63,64-%4"
>    [(set_attr "op_type" "RIE")
>     (set_attr "z10prop" "z10_super_E1")])
> @@ -4182,7 +4187,7 @@ (define_split
>  	(ior:GPR (and:GPR (match_dup 6) (match_dup 5))
>  		 (ashift:GPR (match_dup 3) (match_dup 4))))]
>  {
> -  operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
> +  operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1);
>    if (reg_overlap_mentioned_p (operands[0], operands[3]))
>      {
>        if (!can_create_pseudo_p ())
> @@ -4210,7 +4215,7 @@ (define_split
>  		   (ashift:GPR (match_dup 3) (match_dup 4))))
>       (clobber (reg:CC CC_REGNUM))])]
>  {
> -  operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
> +  operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1);
>    if (reg_overlap_mentioned_p (operands[0], operands[3]))
>      {
>        if (!can_create_pseudo_p ())
> @@ -4412,7 +4417,7 @@ (define_insn "*insv<mode>_mem_reg"
>  {
>      int size = INTVAL (operands[1]) / BITS_PER_UNIT;
>  
> -    operands[1] = GEN_INT ((1ul << size) - 1);
> +    operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1);
>      return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
>  				    : "stcmy\t%2,%1,%S0";
>  }
> @@ -4434,7 +4439,7 @@ (define_insn "*insvdi_mem_reghigh"
>  {
>      int size = INTVAL (operands[1]) / BITS_PER_UNIT;
>  
> -    operands[1] = GEN_INT ((1ul << size) - 1);
> +    operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1);
>      return "stcmh\t%2,%1,%S0";
>  }
>  [(set_attr "op_type" "RSY")
> 
> 	Jakub
>
diff mbox series

Patch

--- gcc/config/s390/s390.md.jj	2019-02-15 18:54:35.037131906 +0100
+++ gcc/config/s390/s390.md	2019-02-15 19:19:02.201945111 +0100
@@ -3917,7 +3917,7 @@  (define_insn "*<risbg_n>_ior_and_sr_ze"
 		 4)))]
   "<z10_or_zEC12_cond>
    && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
-   && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
+   && UINTVAL (operands[2]) == (HOST_WIDE_INT_M1U << UINTVAL (operands[4]))"
   "<risbg_n>\t%0,%3,64-%4,63,%4+%5"
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
@@ -3943,7 +3943,8 @@  (define_insn "*<risbg_n>_and_subregdi_ro
 			     (match_operand:SINT 2 "const_int_operand" "")) 0)
 		(match_operand:DI 3 "contiguous_bitmask_operand" "")))]
   "<z10_or_zEC12_cond>
-   && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))"
+   && (UINTVAL (operands[3])
+       < (HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)))"
   "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
@@ -3955,7 +3956,8 @@  (define_insn "*<risbg_n>_and_subregdi_ro
 			     (match_operand:SINT 2 "const_int_operand" "")) 0)
 		(match_operand:DI 3 "contiguous_bitmask_operand" "")))]
   "<z10_or_zEC12_cond>
-   && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))"
+   && !(UINTVAL (operands[3])
+	& ((HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)) - 1))"
   "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
@@ -3986,7 +3988,8 @@  (define_insn_and_split "*pre_z10_extzv<m
 {
   int bitsize = INTVAL (operands[2]);
   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
-  int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
+  unsigned HOST_WIDE_INT mask
+    = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size);
 
   operands[1] = adjust_address (operands[1], BLKmode, 0);
   set_mem_size (operands[1], size);
@@ -4012,7 +4015,8 @@  (define_insn_and_split "*pre_z10_extv<mo
 {
   int bitsize = INTVAL (operands[2]);
   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
-  int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
+  unsigned HOST_WIDE_INT mask
+    = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size);
 
   operands[1] = adjust_address (operands[1], BLKmode, 0);
   set_mem_size (operands[1], size);
@@ -4116,7 +4120,7 @@  (define_insn "*insv<mode><clobbercc_or_n
 		 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
 			     (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
   "<z10_or_zEC12_cond>
-   && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
+   && UINTVAL (operands[2]) == (HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1"
   "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4"
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
@@ -4131,7 +4135,8 @@  (define_insn "*<risbg_n>_<mode>_ior_and_
 		  (match_operand:GPR 3 "register_operand" "d")
 		  (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
   "<z10_or_zEC12_cond> && UINTVAL (operands[2])
-   == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
+   == (HOST_WIDE_INT_M1U
+       << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
   "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4"
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
@@ -4147,7 +4152,7 @@  (define_insn "*<risbg_n>_sidi_ior_and_ls
 		  (match_operand:DI 3 "register_operand" "d")
 		  (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))]
   "<z10_or_zEC12_cond>
-   && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))"
+   && UINTVAL (operands[2]) == ~(HOST_WIDE_INT_M1U >> UINTVAL (operands[4]))"
   "<risbg_n>\t%0,%3,%4,63,64-%4"
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
@@ -4182,7 +4187,7 @@  (define_split
 	(ior:GPR (and:GPR (match_dup 6) (match_dup 5))
 		 (ashift:GPR (match_dup 3) (match_dup 4))))]
 {
-  operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
+  operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1);
   if (reg_overlap_mentioned_p (operands[0], operands[3]))
     {
       if (!can_create_pseudo_p ())
@@ -4210,7 +4215,7 @@  (define_split
 		   (ashift:GPR (match_dup 3) (match_dup 4))))
      (clobber (reg:CC CC_REGNUM))])]
 {
-  operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
+  operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1);
   if (reg_overlap_mentioned_p (operands[0], operands[3]))
     {
       if (!can_create_pseudo_p ())
@@ -4412,7 +4417,7 @@  (define_insn "*insv<mode>_mem_reg"
 {
     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
 
-    operands[1] = GEN_INT ((1ul << size) - 1);
+    operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1);
     return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
 				    : "stcmy\t%2,%1,%S0";
 }
@@ -4434,7 +4439,7 @@  (define_insn "*insvdi_mem_reghigh"
 {
     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
 
-    operands[1] = GEN_INT ((1ul << size) - 1);
+    operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1);
     return "stcmh\t%2,%1,%S0";
 }
 [(set_attr "op_type" "RSY")