| Message ID | 20190215170029.15641-4-clg@kaod.org |
|---|---|
| State | New |
| Headers | show |
| Series | ppc: add native hash and radix support for POWER9 | expand |
On Fri, Feb 15, 2019 at 06:00:20PM +0100, Cédric Le Goater wrote: > From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > Historically the 64-bit server MMU supports two way of configuring the > guest "real mode" mapping: > > - The "RMA" with is a single chunk of physically contiguous > memory remapped as guest real, and controlled by the RMLS > field in the LPCR register and the RMOR register. > > - The "VRMA" which uses special PTEs inserted in the partition > hash table by the hypervisor. > > POWER9 deprecates the former, which is reflected by the filtering > done in ppc_store_lpcr() which effectively prevents setting of > the RMLS field. > > However, when using fully emulated SPAPR machines, our qemu code > currently only knows how to define the guest real mode memory using > RMLS. > > Thus you cannot run a SPAPR machine anymore with a POWER9 CPU > model today. > > This works around it with a quirk in ppc_store_lpcr() to continue > allowing the RMLS field to be set when using a virtual hypervisor. > > Ultimately we will want to implement configuring a VRMA instead > which will also be necessary if we want to migrate a SPAPR guest > between TCG and KVM but this is a lot more work. Urgh. I'm applying this because it fixes a real bug, but it's not really the right solution. We will want to support VRMAs at some point in order to let emulated powernv machines run guests, but implementing VRMA doesn't really make sense in the context of a PAPR machine. The real problem here is that we're using the LPCR - which notionally doesn't even exist in a PAPR machine - to trick the softmmu code, which is written from the point of view of bare metal - into doing more or less the right thing for a PAPR machine. The correct solution, I think, is to put a test on cpu->vhyp into the guts of the softmmu code so that in non-HV real mode it doesn't even consult the LPCR and just goes directly to GPAs (which is the only think that the pseries machine knows about). Although then I guess we'd need some way in the vhyp of representing the permissible max address of real mode accesses.
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index f1c7729332e6..1175b991d994 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1088,6 +1088,14 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); + /* + * If we have a virtual hypervisor, we need to bring back RMLS. It + * doesn't exist on an actual P9 but that's all we know how to + * configure with softmmu at the moment + */ + if (cpu->vhyp) { + lpcr |= (val & LPCR_RMLS); + } break; default: ;