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[PULL,06/15] target/mips: introduce MTTCG-enabled builds

Message ID 1550166444-22882-7-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series [PULL,01/15] target/mips: compare virtual addresses in LL/SC sequence | expand

Commit Message

Aleksandar Markovic Feb. 14, 2019, 5:47 p.m. UTC 
From: Aleksandar Markovic <amarkovic@wavecomp.com>

Introduce MTTCG-enabled QEMU builds for mips32, mipsn32, and mips64.

Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
 configure         | 3 +++
 target/mips/cpu.h | 2 ++
 2 files changed, 5 insertions(+)
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Patch

diff --git a/configure b/configure
index fbd0825..f0f7518 100755
--- a/configure
+++ b/configure
@@ -7192,11 +7192,13 @@  case "$target_name" in
     target_compiler=$cross_cc_microblaze
   ;;
   mips|mipsel)
+    mttcg="yes"
     TARGET_ARCH=mips
     target_compiler=$cross_cc_mips
     echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak
   ;;
   mipsn32|mipsn32el)
+    mttcg="yes"
     TARGET_ARCH=mips64
     TARGET_BASE_ARCH=mips
     target_compiler=$cross_cc_mipsn32
@@ -7204,6 +7206,7 @@  case "$target_name" in
     echo "TARGET_ABI32=y" >> $config_target_mak
   ;;
   mips64|mips64el)
+    mttcg="yes"
     TARGET_ARCH=mips64
     TARGET_BASE_ARCH=mips
     target_compiler=$cross_cc_mips64
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index eccee37..a10eeb0 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -11,6 +11,8 @@ 
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat.h"
 
+#define TCG_GUEST_DEFAULT_MO (0)
+
 struct CPUMIPSState;
 
 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;